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P102-03SCL Datasheet

  • P102-03SCL

  • Low Skew Output Buffer

  • 6頁(yè)

  • PLL

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PLL102-03
Low Skew Output Buffer
Output-Output Skew
The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the
PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained
from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will
maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; if the
CLK(0-4) is more loaded than CLKOUT, CLK(1-4) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time,
but difference loads cause them to have different rise times and different times crossing
the measurement thresholds.
REF
CLKOUT
CLK(1-4)
Zero Delay
REF input and all outputs loaded equally
REF
CLKOUT
CLK(1-4)
Advanced
REF input and CLK(1-4) outputs loaded equally,
with CLK(1-4) less loaded than CLKOUT.
REF
CLKOUT
CLK(1-4)
Delayed
REF input and CLK(1-4) outputs loaded equally, with
CLK(1-4) more loaded than CLKOUT.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 02/23/06 Page 5

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