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MAX197BCAI+ Datasheet

  • MAX197BCAI+

  • A/D Converter (A-D) IC; Resolution (Bits):12; Sample Rate:10...

  • 604.10KB

  • 16頁

  • Maxim   Maxim

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TIMING CHARACTERISTICS
(V
DD
= 5V
鹵5%;
unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7碌F at REF pin; external clock, f
CLK
= 2.0MHz
with 50% duty cycle; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
CS
Pulse Width
WR
Pulse Width
CS
to
WR
Setup Time
CS
to
WR
Hold Time
CS
to
RD
Setup Time
CS
to
RD
Hold Time
CLK to
WR
Setup Time
CLK to
WR
Hold Time
Data Valid to
WR
Setup
Data Valid to
WR
Hold
RD
Low to Output Data Valid
HBEN High or HBEN Low to
Output Valid
RD
High to Output Disable
RD
Low to
INT
High Delay
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
SYMBOL
t
CS
t
WR
t
CSWS
t
CSWH
t
CSRS
t
CSRH
t
CWS
t
CWH
t
DS
t
DH
t
DO
t
DO1
t
TR
t
INT1
Figure 2, C
L
= 100pF (Note 12)
Figure 2, C
L
= 100pF (Note 12)
(Note 13)
60
0
120
120
70
120
CONDITIONS
MIN
80
80
0
0
0
0
100
50
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX197
Accuracy specifications tested at V
DD
= 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Rejection test. Tested for the 鹵10V input range.
External reference: V
REF
= 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
Ground "on" channel; sine wave applied to all "off" channels.
Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Guaranteed by design. Not tested.
Use static loads only.
Tested using internal reference.
PSRR measured at full-scale.
External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of
WR
with ACQMOD
= high control byte.
Not subject to production testing. Provided for design guidance only.
All input control signals specified with t
R
= t
F
= 5ns from a voltage level of 0.8V to 2.4V.
t
DO
and t
DO1
are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V
or 2.4V.
t
TR
is defined as the time required for the data lines to change by 0.5V.
_______________________________________________________________________________________
5

MAX197BCAI+ 產(chǎn)品屬性

  • Lead (SnPb) Finish for COTSObsolescence Mitigation Program

  • 46

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - ADCs/DAC - 專用型

  • -

  • 數(shù)據(jù)采集系統(tǒng)（DAS）

  • 12 b

  • 100k

  • 并聯(lián)

  • 單電源

  • 4.75 V ~ 5.25 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 28-SSOP（0.209"，5.30mm 寬）

  • 28-SSOP

  • 管件

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