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MAX6953EAX+ Datasheet

  • MAX6953EAX+

  • IC DRVR DSPL LED 36-SSOP

  • 23頁

  • Maxim   Maxim

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2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5
Matrix LED Display Driver
MAX6953
ACKNOWLEDGE FROM MAX6953
HOW COMMAND BYTE AND DATA BYTE MAP INTO
MAX6953'S REGISTERS
ACKNOWLEDGE FROM MAX6953
S
SLAVE ADDRESS
0
A
COMMAND BYTE
A
DATA BYTE
n BYTES
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
鉁?/div>
7
ACKNOWLEDGE FROM MAX6953
D1
D0
A
P
R/W
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 9. n Data Bytes Received
digit appears to flip between two characters. To make a
character appear to blink on or off, write the character
to one plane, and use the blank character (0x20) for the
other plane. Once blinking has been configured, it con-
tinues automatically without further intervention.
Table 3. MAX6953 Address Map
PIN
AD1
GND
GND
GND
GND
V+
V+
V+
V+
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
AD0
GND
V+
SDA
SCL
GND
V+
SDA
SCL
GND
V+
SDA
SCL
GND
V+
SDA
SCL
A6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DEVICE ADDRESS
A4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Blink Speed
The blink speed is determined by frequency of the mul-
tiplex clock, OSC, and by setting the Blink Rate
Selection Bit B (Table 9) in the configuration register.
The Blink Rate Selection Bit B sets either fast or slow
blink speed for the whole display.
Initial Power-Up
On initial power-up, all control registers are reset, the
display is blanked, intensities are set to minimum, and
shutdown is enabled (Table 6).
Configuration Register
The configuration register is used to enter and exit shut-
down, select the blink rate, globally enable and disable
the blink function, globally clear the digit data, and
reset the blink timing (Table 7).
Shutdown Mode (S Data Bit D0) Format
The S bit in the configuration register selects shutdown
or normal operation. The display driver can be pro-
grammed while in shutdown mode, and shutdown mode
is overridden when in the display test mode. For normal
operation, the S bit should be set to 1 (Table 8).
Blink Rate Selection (B Data Bit D2) Format
The B bit in the configuration register selects the blink
rate. This is the speed that the segments alternate
between plane P0 and plane P1 refresh data. The blink
rate is determined by the frequency of the multiplex clock
OSC, in addition to the setting of the B bit (Table 9).
10
______________________________________________________________________________________

MAX6953EAX+ 產(chǎn)品屬性

  • Lead (SnPb) Finish for COTSObsolescence Mitigation Program

  • 30

  • 集成電路 (IC)

  • PMIC - 顯示器驅(qū)動器

  • -

  • LED

  • 5 x 7（矩陣）

  • I²C

  • 4 位數(shù)字

  • 12mA

  • 2.7 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 36-BSOP（0.295"，7.50mm 寬）

  • 36-SSOP

  • 管件

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