最新免费av在线观看,亚洲综合一区成人在线,中文字幕精品无码一区二区三区,中文人妻av高清一区二区,中文字幕乱偷无码av先锋

MAX149BEAP+ Datasheet

  • MAX149BEAP+

  • IC, ADC, 10BIT, 133KSPS, SSOP-20; Resolution (Bits):10; Samp...

  • 24頁

  • Maxim   Maxim

掃碼查看芯片數據手冊

上傳產品規(guī)格書

PDF預覽

+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
CS
SCLK
1
2
3
4
5
UNI/
BIP
6
7
8
9
10
11
12
18
19
20
21
22
23
24
DIN
START
SEL2 SEL1 SEL0
SGL/
DIF PD1
PD0
SSTRB
t
CONV
DOUT
ACQUISITION
1.5碌s
(f
SCLK
= 2MHz)
CONVERSION
7.5碌s MAX
(SHDN = FLOAT)
B9
MSB
B8
B7
B0
LSB
S1
S0
FILLED WITH
ZEROS
A/D STATE
IDLE
IDLE
Figure 9. Internal Clock Mode Timing
CS
t
CONV
t
CSH
SSTRB
t
SSTRB
SCLK
t
DO
PD0 CLOCK IN
DOUT
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
t
SCK
t
CSS
Figure 10. Internal Clock Mode SSTRB Detailed Timing
from the burden of running the SAR conversion clock
and allows the conversion results to be read back at the
processor鈥檚 convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5碌s (SHDN = FLOAT),
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 9).
CS
does
not need to be held low once a conversion is started.
Pulling
CS
high prevents data from being clocked into
the MAX148/MAX149 and three-states DOUT, but it
does not adversely affect an internal clock mode con-
version already in progress. When internal clock mode
is selected, SSTRB does not go into a high-
impedance state when
CS
goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX148/MAX149 at clock rates exceeding 2.0MHz if
the minimum acquisition time (t
ACQ
) is kept above 1.5碌s.
Data Framing
The falling edge of
CS
does
not
start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK鈥檚 falling edge, after the eighth
13
______________________________________________________________________________________

MAX149BEAP+ 產品屬性

  • Lead (SnPb) Finish for COTSObsolescence Mitigation Program

  • 66

  • 集成電路 (IC)

  • 數據采集 - 模數轉換器

  • -

  • 10

  • 133k

  • MICROWIRE?，QSPI?，串行，SPI?

  • 1

  • 640mW

  • 單電源

  • -40°C ~ 85°C

  • 表面貼裝

  • 20-SSOP（0.209"，5.30mm 寬）

  • 20-SSOP

  • 管件

  • 8 個單端，單極；8 個單端，雙極；4 個差分，單極；4 個差分，雙極

MAX149BEAP+相關型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務：
賣家服務：
技術客服：

0571-85317607

網站技術支持

13606545031

客服在線時間周一至周五
9:00-17:30

關注官方微信號，
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務的動力！意見一經采納，將有感恩紅包奉上哦！