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MAX149BEAP+ Datasheet

  • MAX149BEAP+

  • IC, ADC, 10BIT, 133KSPS, SSOP-20; Resolution (Bits):10; Samp...

  • 24頁

  • Maxim   Maxim

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+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
D
Table 3. Channel Selection in Differential Mode (SGL/D
IF
= 0)
SEL2
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
鈥?/div>
+
鈥?/div>
+
鈥?/div>
+
鈥?/div>
+
CH0
+
CH1
鈥?/div>
+
鈥?/div>
+
鈥?/div>
+
鈥?/div>
CH2
CH3
CH4
CH5
CH6
CH7
CS
t
ACQ
SCLK
1
4
SEL2 SEL1 SEL0 UNI/
BIP
START
SGL/ PD1
DIF
8
12
16
20
24
DIN
SSTRB
PD0
RB1
DOUT
ACQUISITION
1.5碌s
(f
SCLK
= 2MHz)
B9
MSB
B8
B7
RB2
B6
B5
B4
B3
B2
B1
B0
LSB
S1
RB3
S0
FILLED WITH
ZEROS
A/D STATE
IDLE
CONVERSION
IDLE
Figure 6. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with f
SCLK
鈮?/div>
2MHz)
Simple Software Interface
Make sure the CPU鈥檚 serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
CS
low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.
6) Pull
CS
high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with one leading zero, two sub-LSB bits, and three trail-
ing zeros. The total conversion time is a function of the
serial-clock frequency and the amount of idle time
between 8-bit transfers. To avoid excessive T/H droop,
make sure the total conversion time does not exceed
120碌s.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 17). For bipolar input mode, the output is twos
complement (Figure 18). Data is clocked out at the
falling edge of SCLK in MSB-first format.
Clock Modes
The MAX148/MAX149 may use either an external
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the external clock shifts data in and out of the
11
______________________________________________________________________________________

MAX149BEAP+ 產(chǎn)品屬性

  • Lead (SnPb) Finish for COTSObsolescence Mitigation Program

  • 66

  • 集成電路 (IC)

  • 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器

  • -

  • 10

  • 133k

  • MICROWIRE?，QSPI?，串行，SPI?

  • 1

  • 640mW

  • 單電源

  • -40°C ~ 85°C

  • 表面貼裝

  • 20-SSOP（0.209"，5.30mm 寬）

  • 20-SSOP

  • 管件

  • 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極

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