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MSP430F2481TRGCR Datasheet

  • MSP430F2481TRGCR

  • Texas Instruments [MIXED SIGNAL MICROCONTROLLER]

  • 1657.04KB

  • TI

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MSP430x23x, MSP430x24x(1), MSP430x2410
MIXED SIGNAL MICROCONTROLLER
SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset
vector (0xFFFE) contains 0xFFFF (e.g., flash is not programmed) the CPU enters LPM4 after power-up.
INTERRUPT SOURCE
Power-up
External reset
Watchdog
Flash key violation
PC out of range (see Note 1)
NMI
Oscillator fault
Flash memory access violation
Timer_B7 (see Note 3)
Timer_B7 (see Note 3)
Comparator_A+
Watchdog timer+
Timer_A3
Timer_A3
INTERRUPT FLAG
PORIFG
WDTIFG
RSTIFG
KEYV
(see Note 2)
NMIIFG
OFIFG
ACCVIFG (see Notes 2 and 7)
TBCCR0 CCIFG
(see Note 4)
TBCCR1 to TBCCR6 CCIFGs,
TBIFG (see Notes 2 and 4)
CAIFG
WDTIFG
TACCR0 CCIFG (see Note 4)
TACCR1 CCIFG
TACCR2 CCIFG
TAIFG (see Note 2 and 4)
UCA0RXIFG, UCB0RXIFG
(see Note 2 and 5)
UCA0TXIFG, UCB0TXIFG
(see Note 2 and 6)
ADC12IFG
(see Notes 2 and 4)
P2IFG.0 to P2IFG.7
(see Notes 2 and 4)
P1IFG.0 to P1IFG.7
(see Notes 2 and 4)
UCA1RXIFG, UCB1RXIFG
(see Note 2)
UCA1TXIFG, UCB1TXIFG
(see Note 2)
Reserved
SYSTEM INTERRUPT
Reset
WORD ADDRESS
0xFFFE
PRIORITY
31, highest
(Non)maskable
(Non)maskable
(Non)maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
0xFFFC
30
0xFFFA
0xFFF8
0xFFF6
0xFFF4
0xFFF2
0xFFF0
29
28
27
26
25
24
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive / transmit
ADC12 (see Note 8)
Maskable
Maskable
Maskable
0xFFEE
0xFFEC
0xFFEA
0xFFE8
23
22
21
20
19
18
17
16
15 to 0 lowest
0,
I/O port P2 (eight flags)
I/O port P1 (eight flags)
USCI A1/B1 receive
USCI A1/B1 transmit
Reserved (see Notes 9 and 10)
Maskable
Maskable
Maskable
Maskable
0xFFE6
0xFFE4
0xFFE2
0xFFE0
0xFFDE to 0xFFC0
NOTES: 1. A reset is executed if the CPU tries to fetch instructions from within the module register memory address range (0x0000 --0x01FF)
or from within unused address ranges.
2. Multiple source flags.
3. Timer_B7 in MSP430F24x(1), MSP430F2410 family has 7 CCRs, Timer_B3 in MSP430F23x family has three CCRs. In Timer_B3,
there are only interrupt flags TBCCR0, 1, and 2 CCIFGs, and the interrupt enable bits TBCCTL0, 1, and 2 CCIE.
4. Interrupt flags are located in the module.
5. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
6. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
7. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot.
8. ADC12 is not implemented in the MSP430F24x1 family.
9. The address 0xFFDE is used as bootstrap loader security key (BSLSKEY).
A 0xAA55 at this location disables the BSL completely.
A zero disables the erasure of the flash if an invalid password is supplied.
10. The interrupt vectors at addresses 0xFFDE to 0xFFC0 are not used in this device and can be used for regular program code if
necessary.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
17

MSP430F2481TRGCR 產(chǎn)品屬性

  • The Ultra-Low Power MSP430MSP430 OverviewMSP430 Design ToolsMSP430 PeripheralsMSP430x2xx/4xx and Wireless OverviewPortable Medical Solutions with MSP430MSP430 for Utility Metering SolutionsMSP430: How to JTAGMSP430, How To Use the Clock SystemGrace Software Graphical User InterfaceMCU OverviewDriver LibraryMSP430Ware Overview

  • 1

  • 集成電路 (IC)

  • 嵌入式 - 微控制器，

  • MSP430F2xx

  • RISC

  • 16-位

  • 16MHz

  • I²C，IrDA，LIN，SCI，SPI，UART/USART

  • 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT

  • 48

  • 48KB（48K x 8 + 256B）

  • 閃存

  • -

  • 4K x 8

  • 1.8 V ~ 3.6 V

  • -

  • 內(nèi)部

  • -40°C ~ 105°C

  • 64-VFQFN 裸露焊盤(pán)

  • Digi-Reel®

  • 296-23083-6

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