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MSP430F247TRGC Datasheet

  • MSP430F247TRGC

  • Texas Instruments [MIXED SIGNAL MICROCONTROLLER]

  • TI

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MSP430x23x, MSP430x24x(1), MSP430x2410
MIXED SIGNAL MICROCONTROLLER
SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007
Port P5 pin schematic: P5.0 to P5.3, input/output with Schmitt trigger
Pad Logic
DVSS
DVCC
P5DIR.x
Module
Direction
0
1
Direction
0: Input
1: Output
0
1
1
P5REN.x
P5OUT.x
Module X OUT
P5SEL.x
P5IN.x
0
1
P5.0/UCB1STE/UCA1CLK
P5.1/UCB1SIMO/UCB1SDA
P5.2/UCB1SOMI/UCB1SCL
P5.3/UCB1CLK/UCA1STE
EN
Module X IN
D
Port P5.0 to P5.3 pin functions
PIN NAME (P5.X)
(P5 X)
P5.0/UCB1STE
鈥?/div>
/
/
UCA1CLK
鈥?/div>
P5.1/UCB1SIMO
鈥?/div>
/
/
UCB1SDA
鈥?/div>
P5.2/UCB1SOMI
鈥?/div>
/
/
UCB1SCL
鈥?/div>
P5.3/UCB1CLK
鈥?/div>
/
/
UCA1STE
鈥?/div>
鈥犫€?/div>
X
0
1
2
3
P5.0 (I/O)
FUNCTION
CONTROL BITS / SIGNALS
P5DIR.x
I: 0; O: 1
X
I: 0; O: 1
X
I: 0; O: 1
X
I: 0; O: 1
X
P5SEL.x
0
1
0
1
0
1
0
1
UCB1STE
鈥?/div>
/UCA1CLK
鈥?/div>
(see Notes 2 and 4)
P5.1 (I/O)
UCB1SIMO
鈥?/div>
/UCB1SDA
鈥?/div>
(see Notes 2 and 3)
P5.2 (I/O)
UCB1SOMI
鈥?/div>
/UCB1SCL
鈥?/div>
(see Notes 2 and 3)
P5.3 (I/O)
UCB1CLK
鈥?/div>
/UCA1STE
鈥?/div>
(see Note 2)
MSP430F24x and MSP430F24x1 devices only
NOTES: 1. X: Don鈥檛 care.
2. The pin direction is controlled by the USCI module.
3. In case the I2C functionality is selected the output drives only the logical 0 to V
SS
level.
4. UCA01CLK function takes precedence over UCB1STE function. If the pin is required as UCA1CLK input or output USCI A/B1 will
be forced to 3--wire SPI mode if 4--wire SPI mode is selected.
78
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265

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