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MSP430F247TRGC Datasheet

  • MSP430F247TRGC

  • Texas Instruments [MIXED SIGNAL MICROCONTROLLER]

  • TI

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MSP430x23x, MSP430x24x(1), MSP430x2410
MIXED SIGNAL MICROCONTROLLER
SLAS547A -- JUNE 2007 -- REVISED NOVEMBER 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs - ports P1, P2, P3, P4, P5, P6, RST/NMI, JTAG, XIN, and XT2IN (see Note 6)
-
PARAMETER
V
IT+
Positive going
Positive-going input threshold voltage
TEST CONDITIONS
VCC
2.2 V
3V
V
IT--
Negative going
Negative-going input threshold voltage
2.2 V
3V
V
hys
R
Pull
C
I
Input voltage hysteresis (V
IT+
-- V
IT--
)
Pullup/pulldown resistor
Input Capacitance
Pullup: V
IN
= V
SS
,
Pulldown: V
IN
= V
CC
V
IN
= V
SS
or V
CC
2.2 V
3V
MIN
0.45 V
CC
1.0
1.35
0.25 V
CC
0.55
0.75
0.2
0.3
20
35
5
TYP
MAX
0.75 V
CC
1.65
2.25
0.55 V
CC
1.2
1.65
1.0
1.0
50
V
k惟
pF
V
V
UNIT
NOTE 6. XIN and XT2IN only in bypass mode
inputs - ports P1 and P2
-
PARAMETER
t
int
External interrupt timing
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, external
trigger pulse width to set the interrupt
flag (see Note 1)
TA0, TA1, TA2
TB0, TB1, TB2, TB3, TB4, TB5, TB6
TACLK, TBCLK,
TACLK TBCLK INCLK: t
(H)
= t
(L)
SMCLK or ACLK signal selected
VCC
2.2 V/3 V
2.2 V
3V
2.2 V
3V
2.2 V
3V
MIN
20
62
50
8
10
8
10
MAX
UNIT
ns
t
cap
f
TAext
f
TBext
f
TAint
f
TBint
Timer_A, Timer_B
Timer A Timer B capture timing
Timer_A, Timer_B clock frequency externally
applied to pin
Timer_A, Timer_B
Timer A Timer B clock frequency
ns
MHz
MHz
NOTE 1. The external signal sets the interrupt flag every time the minimum t
(int)
parameters are met. It may be set even with trigger signals shorter
than t
(int)
.
leakage current - ports P1, P2, P3, P4, P5, and P6 (see Note 1 and 2)
-
PARAMETER
I
lkg(Px.x)
High impedance leakage current
TEST CONDITIONS
See Notes 1 and 2
VCC
2.2 V/3 V
MIN
MAX
鹵50
UNIT
nA
NOTES: 1. The leakage current is measured with V
SS
or V
CC
applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of digital port pins is measured individually. The port pin is selected for input and the pullup/pull--down resistor is
disabled..
standard inputs - RST/NMI
-
PARAMETER
V
IL
V
IH
Low-level input voltage
High-level input voltage
TEST CONDITIONS
VCC
2.2 V/3 V
2.2 V/3 V
MIN
V
SS
0.8 V
CC
MAX
V
SS
+ 0.6
V
CC
UNIT
V
V
36
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265

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