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MSP430F2232IRHAR Datasheet

  • MSP430F2232IRHAR

  • Texas Instruments [MIXED SIGNAL MICROCONTROLLER]

  • TI

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MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504A 鈭?JULY 2006 鈭?REVISED DECEMBER 2006
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh鈭?FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will
go into LPM4 immediately after power-up.
INTERRUPT SOURCE
Power-up
External reset
Watchdog
Flash key violation
PC out-of-range (see Note 1)
NMI
Oscillator fault
Flash memory access violation
Timer_B3
Timer_B3
INTERRUPT FLAG
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 & 4)
TBCCR0 CCIFG (see Note 3)
TBCCR1 and TBCCR2
CCIFGs, TBIFG
(see Notes 2 & 3)
WDTIFG
TACCR0 CCIFG (see Note 3)
TACCR1 CCIFG.
TACCR2 CCIFG
TAIFG (see Notes 2 & 3)
UCA0RXIFG, UCB0RXIFG
(see Notes 2)
UCA0TXIFG, UCB0TXIFG
(see Notes 2)
ADC10IFG (see Note 3)
P2IFG.0 to P2IFG.7
(see Notes 2 & 3)
P1IFG.0 to P1IFG.7
(see Notes 2 & 3)
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Reset
0FFFEh
31, highest
(non)-maskable,
(non)-maskable,
(non)-maskable
maskable
maskable
0FFFCh
30
0FFFAh
0FFF8h
0FFF6h
29
28
27
26
25
24
Watchdog Timer
Timer_A3
Timer_A3
maskable
maskable
maskable
0FFF4h
0FFF2h
0FFF0h
USCI_A0/USCI_B0 Receive
USCI_A0/USCI_B0 Transmit
ADC10
I/O Port P2
(eight flags)
I/O Port P1
(eight flags)
maskable
maskable
maskable
0FFEEh
0FFECh
0FFEAh
0FFE8h
23
22
21
20
19
18
17
16
15
14 ... 0, lowest
maskable
maskable
0FFE6h
0FFE4h
0FFE2h
0FFE0h
(see Note 5)
(see Note 6)
0FFDEh
0FFDCh ... 0FFC0h
NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h鈭?1FFh) or from
within unused address ranges.
2. Multiple source flags
3. Interrupt flags are located in the module
4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
5. This location is used as bootstrap loader security key (BSLSKEY).
A 0AA55h at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
6. The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
13

MSP430F2232IRHAR PDF文件相關(guān)型號

MSP430F2232TRHAT,MSP430F2234IRHAR,MSP430F2234TRHAR,MSP430F2252TDAR,MSP430F2252TRHAR

MSP430F2232IRHAR 產(chǎn)品屬性

  • The Ultra-Low Power MSP430MSP430 OverviewMSP430 Design ToolsMSP430 PeripheralsMSP430x2xx/4xx and Wireless OverviewPortable Medical Solutions with MSP430MSP430 for Utility Metering SolutionsMSP430: How to JTAGMSP430, How To Use the Clock SystemGrace Software Graphical User InterfaceMCU OverviewDriver LibraryMSP430Ware Overview

  • 1

  • 集成電路 (IC)

  • 嵌入式 - 微控制器，

  • MSP430F2xx

  • RISC

  • 16-位

  • 16MHz

  • I²C，IrDA，LIN，SCI，SPI，UART/USART

  • 欠壓檢測/復(fù)位，POR，PWM，WDT

  • 32

  • 8KB（8K x 8 + 256B）

  • 閃存

  • -

  • 512 x 8

  • 1.8 V ~ 3.6 V

  • A/D 12x10b

  • 內(nèi)部

  • -40°C ~ 85°C

  • 40-VFQFN 裸露焊盤

  • Digi-Reel®

  • 296-26205-6

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