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MSP430F2232IDA Datasheet

  • MSP430F2232IDA

  • Texas Instruments [MIXED SIGNAL MICROCONTROLLER]

  • TI

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MSP430x22x2, MSP430x22x4
MIXED SIGNAL MICROCONTROLLER
SLAS504A 鈭?JULY 2006 鈭?REVISED DECEMBER 2006
Terminal Functions, MSP430x22x4 (Continued)
TERMINAL
NAME
P3.5/
UCA0RXD/UCA0SOMI
P3.6/A6/OA0I2
P3.7/A7/OA1I2
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB0/
A12/OA0O
P4.4/TB1
A13/OA1O
P4.5/TB2
A14/OA0I3
P4.6/TBOUTH
A15/OA1I3
P4.7/TBCLK
RST/NMI/SBWTDIO
TEST/SBWTCK
DA
NO.
26
27
28
17
18
19
20
RHA
NO.
24
25
26
15
16
17
18
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DESCRIPTION
General-purpose digital I/O pin
USCI_A0 receive data input in UART mode, slave out/master in in SPI mode
General-purpose digital I/O pin
ADC10 analog input A6 / OA0 analog input I2
General-purpose digital I/O pin
ADC10 analog input A7 / OA1 analog input I2
General-purpose digital I/O pin
Timer_B, capture: CCI0A input, compare: OUT0 output
General-purpose digital I/O pin
Timer_B, capture: CCI1A input, compare: OUT1 output
General-purpose digital I/O pin
Timer_B, capture: CCI2A input, compare: OUT2 output
General-purpose digital I/O pin
Timer_B, capture: CCI0B input, compare: OUT0 output
ADC10 analog input A12 / OA0 analog output
General-purpose digital I/O pin
Timer_B, capture: CCI1B input, compare: OUT1 output
ADC10 analog input A13 / OA1 analog output
General-purpose digital I/O pin
Timer_B, compare: OUT2 output
ADC10 analog input A14 / OA0 analog input I3
General-purpose digital I/O pin
Timer_B, switch all TB0 to TB3 outputs to high impedance
ADC10 analog input A15 / OA1 analog input I3
General-purpose digital I/O pin
Timer_B, clock signal TBCLK input
Reset or nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
Selects test mode for JTAG pins on Port1. The device protection fuse is
connected to TEST.
Spy-Bi-Wire test clock input during programming and test
Digital supply voltage
Analog supply voltage
Digital ground reference
Analog ground reference
NA
QFN package pad connection to DVSS recommended.
21
19
I/O
22
20
I/O
23
21
I/O
24
7
1
22
5
37
I/O
I
I
DVCC
AVCC
DVSS
AVSS
QFN Pad
2
16
4
15
NA
38, 39
14
1, 4
13
Package
Pad
鈥?TDO or TDI is selected via JTAG instruction.
NOTE: If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver
connection to this pad after reset.
10
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265

MSP430F2232IDA PDF文件相關(guān)型號

MSP430F2232TDA,MSP430F2232TRHA,MSP430F2232TRHAR,MSP430F2252IRHAT,MSP430F2254IRHAR,MSP430F2272IRHAT,MSP430F2272TRHA,MSP430F2274IRHA

MSP430F2232IDA 產(chǎn)品屬性

  • The Ultra-Low Power MSP430MSP430 OverviewMSP430 Design ToolsMSP430 PeripheralsMSP430x2xx/4xx and Wireless OverviewPortable Medical Solutions with MSP430MSP430 for Utility Metering SolutionsMSP430: How to JTAGMSP430, How To Use the Clock SystemGrace Software Graphical User InterfaceMCU OverviewDriver LibraryMSP430Ware Overview

  • 40

  • 集成電路 (IC)

  • 嵌入式 - 微控制器，

  • MSP430F2xx

  • RISC

  • 16-位

  • 16MHz

  • I²C，IrDA，LIN，SCI，SPI，UART/USART

  • 欠壓檢測/復(fù)位，POR，PWM，WDT

  • 32

  • 8KB（8K x 8 + 256B）

  • 閃存

  • -

  • 512 x 8

  • 1.8 V ~ 3.6 V

  • A/D 12x10b

  • 內(nèi)部

  • -40°C ~ 85°C

  • 38-TSSOP（0.240"，6.10mm 寬）

  • 管件

  • 296-24121-ND - DEV WRLSS TOOL FOR MSP430296-22904-ND - KIT MSP 430/PROGRAMMER 38PIN

  • 296-26204-5MSP430F2232IDA-ND

MSP430F2232IDA相關(guān)型號PDF文件下載

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