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MC33874BPNA Datasheet

  • MC33874BPNA

  • Freescale Semiconductor, Inc [Quad High-Side Switch (Quad 3...

  • 895.57KB

  • FREESCALE

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FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Any bits clocked out of the Serial Output (SO) pin after the
first 16 bits will be representative of the initial message bits
clocked into the SI pin since the
CS
pin first transitioned to a
logic [0]. This feature is useful for daisy-chaining devices as
well as message verification.
A valid message length is determined following a
CS
transition of [0] to [1]. If there is a valid message length, the
data is latched into the appropriate registers. A valid
message length is a multiple of 16 bits. At this time, the SO
pin is tri-stated and the fault status register is now able to
accept new fault status information.
SO data will represent information ranging from fault
status to register contents, user selected by writing to the
STATR bits OD4, OD3, OD2, OD1, and OD0. The value of
the previous bits SOA4 and SOA3 will determine which
output the SO information applies to for the registers which
are output specific; viz., Fault, SOCHLR, CDTOLR, and
DICR registers.
Note that the SO data will continue to reflect the
information for each output (depending on the previous OD4,
OD3 state) that was selected during the most recent STATR
write until changed with an updated STATR write.
The output status register correctly reflects the status of
the STATR-selected register data at the time that the
CS
is
pulled to a logic [0] during SPI communication, and/or for the
period of time since the last valid SPI communication, with
the following exceptions:
鈥?The previous SPI communication was determined to be
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
鈥?Battery transients below 6.0 V resulting in an under-
voltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI
communication following an undervoltage V
PWR
condition should be ignored.
鈥?The
RST
pin transition from a logic [0] to [1] while the
WAKE pin is at logic [0] may result in incorrect data
loaded into the Status register. The SO data transmitted
to the MCU during the first SPI communication following
this condition should be ignored.
SERIAL OUTPUT BIT ASSIGNMENT
The 16 bits of serial output data depend on the previous
serial input message, as explained in the following
paragraphs.
Table 16,
page
25,
summarizes SO returned
data for bits OD15 : OD0.
鈥?Bit OD15 is the MSB; it reflects the state of the
Watchdog bit from the previously clocked-in message.
鈥?Bit OD14 remains logic [0] except when an
undervoltage condition occurred.
鈥?Bit OD13 remains logic [0] except when an overvoltage
condition occurred.
鈥?Bits OD12 : OD8 reflect the state of the bits
SOA4 : SOA0 from the previously clocked in message.
鈥?Bits OD7 : OD4 give the fault status flag of the outputs
HS3 : HS0, respectively.
鈥?The contents of bits OD3 : OD0 depend on bits D4 : D0
from the most recent STATR command SOA4 : SOA0
as explained in the paragraphs following
Table 16.
33874
24
Analog Integrated Circuit Device Data
Freescale Semiconductor

MC33874BPNA PDF文件相關(guān)型號

MC33874BPNAR2

MC33874BPNA 產(chǎn)品屬性

  • 168

  • 集成電路 (IC)

  • PMIC - MOSFET，電橋驅(qū)動器 - 內(nèi)部開關(guān)

  • -

  • 高端

  • SPI

  • 4

  • 35 毫歐

  • -

  • -

  • 6 V ~ 27 V

  • -40°C ~ 125°C

  • 表面貼裝

  • 24-PowerQFN

  • 24-PQFN（12x12）

  • 托盤

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