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MC33874BPNA Datasheet

  • MC33874BPNA

  • Freescale Semiconductor, Inc [Quad High-Side Switch (Quad 3...

  • 895.57KB

  • FREESCALE

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FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
detection levels, defined by I
OCH
and I
OCL
, are illustrated in
Figure 6,
page
13.
The eight different overcurrent low detect
levels (I
OCL0
: I
OCL7
) are illustrated in
Figure 6.
If the load current level ever reaches the selected
overcurrent low detection level and the overcurrent condition
exceeds the programmed overcurrent time period (t
OC
x
), the
device will latch the output OFF.
If at any time the current reaches the selected I
OCH
level,
then the device will immediately latch the fault and turn OFF
the output, regardless of the selected t
OCH
driver.
For both cases, the device output will stay off indefinitely
until the device is commanded OFF and then ON again.
UNDERVOLTAGE SHUTDOWN (LATCHING OR
NON-LATCHING)
The output(s) will latch off at some battery voltage below
6.0 V. As long as the V
DD
level stays within the normal
specified range, the internal logic states within the device will
be sustained.
In the case where battery voltage drops below the
undervoltage threshold (V
PWRUV
) output will turn off, FS will
go to logic 0, and the fault register UVF bit will be set to 1.
Two cases need to be considered when the battery level
recovers :
鈥?If outputs command are low, FS will go to logic 1 but the
UVF bit will remain set to 1 until the next read operation
(warning report).
鈥?If the output command is ON, then FS will remain at
logic 0. The output must be turned OFF and ON again
to re-enable the state of output and release FS. The
UVF bit will remain set to 1 until the next read operation.
The undervoltage protection can be disabled through SPI
(bit UV_dis = 1). In this case, the FS does not report any
undervoltage fault condition, UVF bit is set to 1, and the
output state is not changed as long as the battery voltage
does not drop any lower than 2.5 V.
The daisy chain feature is available under VDD in nominal
conditions.
OVERVOLTAGE FAULT (NON-LATCHING)
The 33874 shuts down the output during an overvoltage
fault (OVF) condition on the VPWR pin. The output remains
in the OFF state until the overvoltage condition is removed.
When experiencing this fault, the OVF fault bit is set in the bit
D1 and cleared after either a valid SPI read or a power reset
of the device.
The overvoltage protection can be disabled through SPI
(bit OV_DIS). When disabled, the returned SO bit OD13 still
reflects any overvoltage condition (overvoltage warning).
33874
Analog Integrated Circuit Device Data
Freescale Semiconductor
19

MC33874BPNA PDF文件相關(guān)型號

MC33874BPNAR2

MC33874BPNA 產(chǎn)品屬性

  • 168

  • 集成電路 (IC)

  • PMIC - MOSFET，電橋驅(qū)動器 - 內(nèi)部開關(guān)

  • -

  • 高端

  • SPI

  • 4

  • 35 毫歐

  • -

  • -

  • 6 V ~ 27 V

  • -40°C ~ 125°C

  • 表面貼裝

  • 24-PowerQFN

  • 24-PQFN（12x12）

  • 托盤

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