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MC33874BPNA Datasheet

  • MC33874BPNA

  • Freescale Semiconductor, Inc [Quad High-Side Switch (Quad 3...

  • FREESCALE

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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
SPI PROTOCOL DESCRIPTION
The SPI interface has a full duplex, three-wire
synchronous data transfer with four I/O lines associated with
it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK),
and Chip Select (
CS
).
The SI / SO pins of the 33874 follow a first-in first-out (D15
to D0) protocol, with both input and output words transferring
the most significant bit (MSB) first. All inputs are compatible
with 5.0 V CMOS logic levels.
CSB
CS
CS
SCLK
SI
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD15 OD14 OD13 OD12 OD11 OD10 OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1 OD0
Notes 1.
RST
is a logic [1] state during the above operation.
NOTES: 1.
2. D15
is
D0 relate
state during the
recent ordered entry of data into the device.
RSTB
:
in a logic H
to the most
above operation.
out of
2.
3. OD15
D2, ... , and D15
to the first
most
bits of
ordered entry of program data into the LUX IC
the device.
DO, D1,
:
OD0 relate
relate to the
16
recent
ordered fault and status data
device.
Figure 9. Single 16-Bit Word SPI Communication
OPERATIONAL MODES
The 33874 has four operating modes: Sleep, Normal,
Fault, and Fail-Safe.
Table 5
summarizes details contained in
succeeding paragraphs.
Table 5. Fail-Safe Operation and Transitions to Other
33874 Modes
Mode
Sleep
Normal
Fault
FS
x
1
0
0
0
1
1
1
Fail-
Safe
Wake RST WDTO
0
x
1
1
0
0
1
1
0
1
1
0
1
1
1
0
Yes
x
No
No
Comments
Device is in Sleep mode. All
outputs are OFF
Normal mode. Watchdog is
active if enabled.
Device is currently in fault
mode. The faulted output(s)
is (are) OFF.
Watchdog has timed out and
the device is in Fail-Safe
Mode. The outputs are as
configured with the RFS
resistor connected to FSI.
RST
and WAKE must go
from logic [1] to logic [0]
simultaneously to bring the
device out of the Fail-safe
mode or momentarily tied the
FSI pin to ground.
SLEEP MODE
The Default mode of the 33874 is the Sleep mode. This is
the state of the device after first applying battery voltage
(V
PWR
) prior to any I/O transitions. This is also the state of the
device when the WAKE and
RST
are both logic [0]. In the
Sleep mode, the output and all unused internal circuitry, such
as the internal 5.0 V regulator, are off to minimize current
draw. In addition, all SPI-configurable features of the device
are as if set to logic [0]. The 33874 will transition to the
Normal or Fail-Safe operating modes based on the WAKE
and
RST
inputs as defined in
Table 5.
NORMAL MODE
The 33874 is in Normal mode when:
鈥?V
PWR
and V
DD
are within the normal voltage range.
鈥?/div>
RST
pin is logic [1].
鈥?No fault has occurred.
FAIL-SAFE MODE
FAIL-SAFE MODE AND WATCHDOG
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or
RST
input pin
transitions from logic [0] to logic [1]. The WAKE input is
capable of being pulled up to V
PWR
with a series of limiting
33874
x = Don鈥檛 care.
Analog Integrated Circuit Device Data
Freescale Semiconductor
17

MC33874BPNA PDF文件相關(guān)型號

MC33874BPNAR2

MC33874BPNA 產(chǎn)品屬性

  • 168

  • 集成電路 (IC)

  • PMIC - MOSFET,電橋驅(qū)動(dòng)器 - 內(nèi)部開關(guān)

  • -

  • 高端

  • SPI

  • 4

  • 35 毫歐

  • -

  • -

  • 6 V ~ 27 V

  • -40°C ~ 125°C

  • 表面貼裝

  • 24-PowerQFN

  • 24-PQFN(12x12)

  • 托盤

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