MC12181
APPLICATIONS INFORMATION
The MC12181 is intended for applications where a fixed
LO, or a limited number of local oscillator frequencies is
required to be synthesized. The device acts as a x25 鈥?40
PLL. The 4鈥揵it parallel interface allows 1 of 16 divide ratios to
be selected. Internally there are fixed divide by 8 prescalers
in the reference and programmable paths of the PLL. The
MC12181 operates from 125 MHz to 1000 MHz which makes
the part ideal for FCC Title 47; Part 15 applications in the 260
MHz to 470 MHz band and the 902 to 928 MHz Band.
Figure 4 shows a typical block diagram of the application.
Figure 4. Typical Block Diagram of Complete PLL
External
Ref
10.0MHz
梅8
MC12181 PLL
蠁/Freq
Det
Charge
Pump
Loop
Filter
VCO
250鈥?00
MHz
OSCout
OSCin
To Phase/
Frequency
Detector
minimizing EMI and switching noise which can be generated
by rail鈥搕o鈥搑ail CMOS outputs. The OSCout output should not
be used to drive other circuitry.
The oscillator buffer in the MC12181 is a single stage, high
speed, differential input/output amplifier; it may be
considered to be a form of the Pierce oscillator. A simplified
circuit diagram is seen in Figure 5.
Figure 5. Simplified Crystal Oscillator/Buffer Circuit
VCC
梅N
25鈥?0
Bias
Source
梅8
As can be seen from the block diagram, with the addition
of a VCO, a loop filter, and either an external oscillator or
crystal, a complete PLL sub鈥搒ystem can be realized. Since
most of the PLL functions are integrated into the 12181, the
users focus is on the loop filter design and the crystal
reference oscillator circuit.
Crystal Oscillator Design
The PLL is used to transfer the high stability characteristic
of a low frequency reference source to the high frequency
VCO within the PLL loop. To facilitate this, the device
contains an input circuit which can be configured as a crystal
oscillator or a buffer for accepting an external signal source.
In the external reference mode, the reference source is
ac鈥揷oupling into the OSCin input pin. The level of this signal
should be between 500 鈥?2200 mVp鈥損. An external low noise
reference should be used when it is desired to obtain the best
close鈥搃n phase noise performance for the PLL. In addition the
input reference amplitude should be close to the upper
amplitude specification. This maximizes the slew rate of the
input signal as it switches against the internal voltage
reference.
In the crystal mode, an external parallel鈥搑esonant
fundamental mode crystal should be connected between the
OSCin and OSCout pins. This crystal must be between 5 and
25 MHz. External capacitors C1 and C2, as shown in
Figure 2, are required to set the proper crystal load
capacitance and oscillator frequency. The values of the
capacitors are dependent on the crystal choosen and the
input capacitance of the device as well as stray board
capacitance.
Since the MC12181 is realized with an all鈥揵ipolar ECL
style design, the internal oscillator circuitry is different from
more traditional CMOS oscillator designs which realize the
crystal oscillator with a modified inverter topology. These
CMOS designs typically excite the crystal with a rail鈥搕o鈥搑ail
signal which may overdrive the crystal resulting in damage or
unstable operation. The MC12181 design does not exhibit
this phenomena because the swing out of the OSCout pin is
less than 600 mVp鈥損. This has the added advantage of
OSCin drives the base of one input of an NPN transistor
differential pair. The non鈥搃nverting input of the differential pair
is internally biased. OSCout is the inverted input signal and is
buffered by an emitter follower with a 70
碌A(chǔ)
pull鈥揹own
current and has a voltage swing of about 600mVp鈥損. Open
loop output impedance is approximately 425
鈩?
The opposite
side of the differential amplifier output is used internally to
drive another buffer stage which drives the phase/frequency
detector. With the 50 k鈩?feedback resistor in place, OSCin
and OSCout are biased to approximately 1.1 V below VCC.
The amplifier has a voltage gain of about 15dB and a
bandwidth in excess of 150 MHz. Adherence to good RF
design and layout techniques, including power supply pin
decoupling, is strongly recommended.
A typical crystal oscillator application is shown in Figure 2.
The crystal and the feedback resistor are connected directly
between OSCin and OSCout, while the loading capacitors, C1
and C2, are connected between OSCin and ground, and
OSCout and ground respectively. It is important to understand
that as far as the crystal is concerned, the two loading
capacitors are in series (albeit through ground). So when the
crystal specification defines a specific loading capacitance,
this refers to the total external (to the crystal) capacitance
seen across its two pins.
This capacitance consists of the capacitance contributed
by the amplifier (IC and packaging), layout capacitance, and
the series combination of the two loading capacitors. This is
illustrated in the equation below:
CI
+
CAMP
)
CSTRAY
)
C1
)
C2
C1 C2
Provided the crystal and associated components are
located immediately next to the IC, thus minimizing the stray
capacitance, the combined value of CAMP and CSTRAY is
approximately 5pF. Note that the location of the OSCin and
OSCout pins at the end of the package, facilitates placing the
crystal, resistor and the C1 and C2 capacitors very close to
the device. Usually, one of the capacitors is in parallel with an
adjustable capacitor used to trim the frequency of oscillation.
5
MOTOROLA RF/IF DEVICE DATA
MOTOROLA
1
2
3
4
5
6
7
8
9
