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M5-128/104-10VC Datasheet

  • M5-128/104-10VC

  • Lattice Semiconductor [Fifth Generation MACH Architecture]

  • 1087.46KB

  • LATTICE   LATTICE

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

Clock Line 1 Options
x
Global clock (0, 1, 2, or 3) with positive edge clock enable
x
Global clock (0, 1, 2, or 3) with negative edge clock enable
x
Global clock (0, 1, 2, or 3) with positive and negative edge clock enable (biphase)
Clock Line 2 Options
x
Global clock (0, 1, 2, or 3) with clock enable
Clock Line 3 Options
x
Complement of clock line 2 (same clock enable)
x
Product-term clock (if clock line 2 does not use clock enable
PT (0:3)
PINCLK (0:3)
0
1
2
3
MUX 4TO1
IN (0)
IN (1)
IN (2) OUT
IN (3)
U1
F1
F0
MUX 2TO1
CLKIN
Clock Enable
PT0
N (0)
OUT
N (1)
F0
/CLK
F0
MUX 2TO1
CLK0
PT (0:2)
PT0
MUX 4TO1
0
1
2
3
IN (0)
IN (1)
IN (2) OUT
IN (3)
U2
F1
F0
/CLK
CLK1
CLK
PT1
PT2
CLKEN1
BIPHASE
CLKEN2
OUT
SET0/RST0
MUX 2TO1
PT1
PT1
OUT
/PT1(ST)
F0
SET1/RST1
MUX 2TO1
MUX 4TO1
0
1
2
3
IN (0)
IN (1)
IN (2) OUT
IN (3)
U3
F1
F0
PT3
MUX 2TO1
/CLK2
PTCLK
F0
CLK3
CLK2
CLKIN
Clock Enable
MUX
2TO1
PT2
PT2
OUT
/PT2
F0
SET2/RST2/LE
Block
Sets/Reset
0鈥?, LE
Block
Clocks
0鈥?
20446G-004
20446G-005
Figure 4. Clock Generator
Figure 5. Set/Reset Generator
The set/reset generation portion of the control generator (Figure 5) creates three set/reset lines for
the PAL block. Each macrocell can choose one of these three lines or choose no set/reset at all.
All three lines can be con鏗乬ured for product term set/reset and two of the three lines can be
con鏗乬ured as sum term set/reset and one of the lines can be con鏗乬ured as product-term or sum-
term latch enable. While the set/reset signals are generated in the control generator, whether that
signal sets or resets a 鏗俰p-鏗俹p is determined within the individual macrocell. The same signal can
set one 鏗俰p-鏗俹p and reset another. PT2 or /PT2 can also be used as a latch enable for macrocells
con鏗乬ured as latches.
MACH 5 Family
7

M5-128/104-10VC PDF文件相關(guān)型號

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