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M5-128/104-10VC Datasheet

  • M5-128/104-10VC

  • Lattice Semiconductor [Fifth Generation MACH Architecture]

  • LATTICE   LATTICE

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Macrocells
The macrocells for MACH 5 devices consist of a storage element which can be con鏗乬ured for
combinatorial, registered or latched operation (Figure 3). The D-type 鏗俰p-鏗俹ps can be con鏗乬ured
as T-type, J-K, or S-R operation through the use of the XOR gate associated with each macrocell.
Each PAL block has the capability to provide two input registers by using macrocells 0 and 15. In
order to use this option, these macrocells must be accessed via the I/O pins associated with
macrocells 3 and 12, respectively. Once the macrocell is used as an input register, it cannot be used
for logic, so its clusters can be re-directed through the logic allocator to another macrocell. The
I/O pins associated with macrocells 0 and 15 can still be used as input pins. Although the I/O pins
for macrocells 3 and 12 are used to connect to the input registers, these macrocells can still be
used as 鈥渂uried鈥?macrocells to drive device logic via the matrix.
Control Bus
Macrocell
Logic
Allocator
5-8
Clusters/
MC
D
Q
Prog. Polarity
Mode
Selection
20446G-003
Figure 3. Macrocell Diagram
Control Generator
The control generator provides four con鏗乬urable clock lines and three con鏗乬urable set/reset lines to
each macrocell in a PAL block. Any of the four clock lines and any of the three set/reset lines can
be independently selected by any 鏗俰p-鏗俹p within a block. The clock lines can be con鏗乬ured to
provide synchronous global (pin) clocks and asynchronous product term clocks, sum term clocks,
and latch enables (Figure 4). Three of the four global clocks, as well as two product-term clocks
and one sum-term clock, are available per PAL block. Positive or negative edge clocking is
available as well as advanced clocking features such as
complementary
and
biphase
clocking.
Complementary clocking provides two clock lines exactly 180 degrees out of phase, and is useful
in applications such as fast data paths. A biphase clock line clocks 鏗俰p-鏗俹ps on both the positive
and negative edges of the clock. The con鏗乬uration options for the four clock lines per PAL block
are as follows:
Clock Line 0 Options
x
Global clock (0, 1, 2, or 3) with positive or negative edge clock enable
x
Product-term clock (A*B*C)
x
Sum-term clock (A+B+C)
6
MACH 5 Family

M5-128/104-10VC PDF文件相關(guān)型號

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