鈥?鈥?/div>
Main clock division ratio selection bit (Note 3)
Middle-speed mode
High-speed mode
or Low-speed mode
Main clock stop bit (Note 3)
Timing
蠁
(Internal clock)
Q
S
R
STP instruction
WIT
instruction
S
R
Q
Q
S
R
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Notes 1 :
When selecting the low-speed mode, set the port X
C
switch bit to 鈥?鈥?
2 :
Refer to the structure of timer 12 mode register.
3 :
Refer to the structure of CPU mode register (next page).
Fig. WA-3 Clock generating circuit block diagram
48