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M38192M5-XXXFS Datasheet

  • M38192M5-XXXFS

  • Mitsubishi Electric Semiconductor [SINGLE-CHIP 8-BIT CMOS M...

  • MITSUBISHI   MITSUBISHI

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MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPT INTERVAL DETERMINATION
FUNCTION
The 3819 group builds in an interrupt interval determination circuit.
This interrupt interval determination circuit has an 8-bit binary up
counter. Using this counter, it determines a duration of time from
the rising transition (falling transition) of an input signal pulse on
the P4
2
/INT
2
pin to the rising transition (falling transition) of the
signal pulse that is input next.
How to determine the interrupt interval is described below.
聦Enable
the INT
2
interrupt by setting the bit 2 of the interrupt con-
trol register 1 (address 003E
16
). Select the rising interval or
falling interval by setting the bit 2 of the interrupt edge selection
register (address 003A
16
).
聧
Set the bit 0 of the interrupt interval determination control regis-
ter (address 0031
16
) to 鈥?鈥?(interrupt interval determination
operating).
聨Select
the sampling clock of 8-bit binary up counter by setting
the bit 1 of the interrupt interval determination control register.
When writing 鈥?鈥? f(X
IN
)/256 is selected (the sampling interval:
32
碌s
at f(X
IN
) = 8.38 MHz) ; when 鈥?鈥? f(X
IN
)/512 is selected (the
sampling interval: 64
碌s
at f(X
IN
) = 8.38 MHz).
聫
When the signal of polarity which is set on the INT
2
pin (rising or
falling transition) is input, the 8-bit binary up counter starts
counting up of the selected counter sampling clock.
聬When
the signal of polarity above
聫
is input again, the value of
the 8-bit binary up counter is transferred to the interrupt interval
determination register (address 0030
16
), and the remote control
interrupt request occurs. Immediately after that, the 8-bit binary
up counter is cleared to 鈥?0
16
鈥? The 8-bit binary up counter con-
tinues to count up again from 鈥?0
16
鈥?
聭When
count value reaches 鈥淔F
16
鈥? the 8-bit binary up counter
stops counting up. Then, simultaneously when the next counter
sampling clock is input, the counter sets value 鈥淔F
16
鈥?to the in-
terrupt interval determination register to generate the counter
overflow interrupt request.
Noise filter
The P4
2
/INT
2
pin builds in the noise filter.
The noise filter operation is described below.
聦Select
the sampling clock of the input signal with the bits 2 and
3 of the interrupt interval determination control register. When
not using the noise filter, set 鈥?0
2
鈥?
聧The
P4
2
/INT
2
input signal is sampled in synchronization with the
selected clock. When sampling the same level signal in series,
the signal is recognized as the interrupt signal, and the interrupt
request occurs.
When setting the bit 4 of interrupt interval determination control
register to 鈥?鈥? the interrupt request can occur at both rising and
falling edges.
When using the noise filter, set the minimum pulse width of the
INT
2
input signal to 2 cycles or more.
Note :
In the low-speed mode (CM
7
=1), the interrupt interval determination
function can not operate.
The counter
sampling clock
selection bit
f(X
IN
)/256
f(X
IN
)/512
8-bit binary up counter
The counter overflow
interrupt request or
remote control interrupt request
INT
2
interrupt input
Noise filter
Interrupt interval
determination register
address 0030
16
Noise filter sampling
clock selection bit
1/64 1/128
Divider
One-sided/both-sided
detection selection bit
1/256
Data bus
f(X
IN
)
Fig. DE-1 Block diagram of interrupt interval datermination circuit
40

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