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LP3907SQX-PXPP Datasheet

  • LP3907SQX-PXPP

  • Intersil Corporation [Dual High-Current Step-Down DC/DC and...

  • INTERSIL   INTERSIL

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LP3907
EN_DLY PRESET DELAY SEQUENCE AFTER EN_T ASSERTION
EN_DLY<2:0>
000
001
010
011
100
101
110
111
Delay (ms)
Buck1
1
1
1.5
1.5
1.5
1.5
3
2
Buck2
1
1.5
2
2
2
1.5
2
3
LDO1
1
2
3
1
3
2
1
6
LDO2
1
2
6
1
6
2
1.5
11
BUCK AND LDO OUTPUT VOLTAGE ENABLE REGISTER (BKLDOEN) 鈥?0X10
This register controls the enables for the Bucks and LDOs.
D7
Name
Access
Data
Reset
鈥?/div>
鈥?/div>
Reserved
0
D6
LDO2EN
R/W
0 鈥?Disable
1 鈥?Enable
1
D5
鈥?/div>
鈥?/div>
Reserved
1
D4
LDO1EN
R/W
0 鈥?Disable
1 鈥?Enable
1
D3
鈥?/div>
鈥?/div>
Reserved
0
D2
BK2EN
R/W
0 鈥?Disable
1 鈥?Enable
1
D1
鈥?/div>
鈥?/div>
Reserved
0
D0
BK1EN
R/W
0 鈥?Disable
1 鈥?Enable
1
BUCK AND LDO STATUS REGISTER (BKLDOSR) 鈥?0X11
This register monitors whether the Bucks and LDOs meet the voltage output specifications.
D7
Name
Access
Data
BKS_OK
R
0 鈥?Buck 1-2
Not Valid
1 鈥?Bucks
Valid
0
D6
LDOS_OK
R
D5
LDO2_OK
R
D4
LDO1_OK
R
D3
鈥?/div>
鈥?/div>
D2
BK2_OK
R
D1
鈥?/div>
鈥?/div>
D0
BK1_OK
R
0 鈥?Buck1 Not
Valid
1 鈥?Buck1
Valid
0
0 鈥?LDO 1-2
0 鈥?LDO2 Not 0 鈥?LDO1 Not Reserve
Not Valid
Valid
Valid
d
1 鈥?LDOs Valid 1 鈥?LDO2 Valid 1 鈥?LDO1 Valid
0
0
0
0
0 鈥?Buck2 Not Reserve
Valid
d
1 鈥?Buck2
Valid
0
0
Reset
BUCK VOLTAGE CHANGE CONTROL REGISTER 1 (VCCR) 鈥?0X20
This register selects and controls the output target voltages for the buck regulators.
D7-6
Name
Access
Data
鈥?/div>
鈥?/div>
Reserved
D5
B2VS
R/W
Buck2 Target Voltage
Select
0 鈥?B2VT1
1 鈥?B2VT2
0
D4
B2GO
R/W
D3-2
鈥?/div>
鈥?/div>
D1
B1VS
R/W
Buck1 Target Voltage
Select
0 鈥?B1VT1
1 鈥?B1VT2
0
D0
B1GO
R/W
Buck1 Voltage Ramp
CTRL
0 鈥?Hold
1 鈥?Ramp to B1VS
selection
0
Buck2 Voltage Ramp Reserved
CTRL
0 鈥?Hold
1 鈥?Ramp to B2VS
selection
0
00
Reset
00
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