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LP3907SQX-PXPP Datasheet

  • LP3907SQX-PXPP

  • Intersil Corporation [Dual High-Current Step-Down DC/DC and...

  • INTERSIL   INTERSIL

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LP3907
I
2
C Compatible Serial Interface
I
2
C SIGNALS
The LP3907 features an I
2
C compatible serial interface, using
two dedicated pins: SCL and SDA for I
2
C clock and data re-
spectively. Both signals need a pull-up resistor according to
the I
2
C specification. The LP3907 interface is an I
2
C slave that
is clocked by the incoming SCL clock.
Signal timing specifications are according to the I
2
C bus spec-
ification. The maximum bit rate is 400kbit/s. See I
2
C specifi-
cation from Philips for further details.
I
2
C DATA VALIDITY
The data on the SDA line must be stable during the HIGH
period of the clock signal (SCL), e.g.- the state of the data line
can only be changed when CLK is LOW.
30017816
I
2
C Signals: Data Validity
to HIGH while the SCL is HIGH. The
2
C master always gen-
I
2
C START AND STOP CONDITIONS
erates START and STOP bits. The I2C bus is considered to
START and STOP bits classify the beginning and the end of
be busy after START condition and free after STOP condition.
the I
2
C session. START condition is defined as the SDA signal
During data transmission, I
2
C master can generate repeated
transitioning from HIGH to LOW while the SCL line is HIGH.
START conditions. First START and repeated START condi-
STOP condition is defined as the SDA transitioning from LOW
tions are equivalent, function-wise.
30017817
START and STOP Conditions
27
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