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LP3907SQX-PXPP Datasheet

  • LP3907SQX-PXPP

  • Intersil Corporation [Dual High-Current Step-Down DC/DC and...

  • INTERSIL   INTERSIL

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LP3907
Design Implementation of the Flexible Power-On Reset
30017812
An internal Power-on reset of the IC is used with EN1, and
EN2 to produce a reset signal (LOW) to the delay timer nPOR.
EN1 and RDY1 or EN2 and RDY2 are used to generate the
set signal (HIGH) to the delay timer. S=R=1 never occurs. The
mask timers are triggered off EN1 and EN2 which are gated
with RDY1, and RDY2 to generate outputs to the final AND
gate to generate the nPOR.
Under Voltage Lock Out
The LP3907 features an 鈥渦nder voltage lock out circuit鈥? The
function of this circuit is to continuously monitor the raw input
supply voltage (VINLDO12) and automatically disables the
four voltage regulators whenever this supply voltage is less
than 2.8VDC.
The circuit incorporates a bandgap based circuit that estab-
lishes the reference used to determine the 2.8VDC trip point
for a V
IN
OK 鈥?Not OK detector. This V
IN
OK signal is then
used to gate the enable signals to the four regulators of the
LP3907. When VINLDO12 is greater than 2.8VDC the four
enables control the four regulators, when VINLDO12 is less
than 2.8VDC the four regulators are disabled by the V
IN
de-
tector being in the 鈥淣ot OK鈥?state. The circuit has built in
hysteresis to prevent chattering occurring.
www.national.com
26

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