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LP3907SQX-PXPP Datasheet

  • LP3907SQX-PXPP

  • Intersil Corporation [Dual High-Current Step-Down DC/DC and...

  • INTERSIL   INTERSIL

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LP3907
DC/DC Converters
OVERVIEW
The LP3907 supplies the various power needs of the application by means of two Linear Low Drop Regulators (LDO1 and LDO2)
and two Buck converters (SW1 and SW2). The table hereunder lists the output characteristics of the various regulators.
Supply Specification
Output
Supply
Load
V
OUT
Range(V)
1.0 to 3.5
1.0 to 3.5
0.8 to 2.0
1.0 to 3.5
Resolution (mV)
100
100
50
100
I
MAX
Maximum Output
Current (mA)
300
300
1000
600
LDO1
LDO2
SW1
SW2
analog
analog
digital
digital
*For default values of the regulators, please consult page 3 of this datasheet.
LINEAR LOW DROPOUT REGULATORS (LDOS)
LDO1 and LDO2 are identical linear regulators targeting ana-
log loads characterized by low noise requirements. LDO1 and
LDO2 are enabled through the ENLDO pin or through the
corresponding LDO1 or LDO2 control register. The output
voltages of both LDOs are register programmable. The de-
fault output voltages are factory programmed during Final
Test, which can be tailored to the specific needs of the system
designer.
30017822
NO-LOAD STABILITY
The LDOs will remain stable and in regulation with no external
load. This is an important consideration in some circuits, for
example, CMOS RAM keep-alive applications.
LDO1 AND LDO2 CONTROL REGISTERS
LDO1 and LDO2 can be configured by means of the LDO1
and LDO2 control registers. The output voltage is pro-
grammable in steps of 100mV from 1.0V to 3.5V by program-
ming bits D4-0 in the LDO Control registers. Both LDO1 and
LDO2 are enabled by applying a logic 1 to the ENLDO1 and
ENLDO2 pin. Enable/disable control is also provided through
enable bit of the LDO1 and LDO2 control registers. The value
of the enable LDO bit in the register is logic 1 by default. The
output voltage can be altered while the LDO is enabled.
17
www.national.com

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