鈮?/div>
鹵
200V
鈭?.3V to +4.0V
鈭?.3V to +4.0V
鈭?.3V to +4.0V
鈭?.3V to (V
DDIO
+0.3V)
鈭?.3V to (V
DDA
+0.3V)
+150藲C
鈭?5藲C to +150藲C
Maximum Package Power Dissipation Capacity at 25藲C
UFBGA Package (Note 4)
Derate UFBGA Package above
25藲C
Theta JA
LLP Package (Note 4)
Derate LLP Package above 25藲C
Theta JA
2.5 W
25 mW/藲C
45藲C/W
1.39 W
11 mW/藲C
90藲C/W
Recommended Operating
Conditions
Min Typ Max
Supply Voltage
V
DDA
to V
SSA
and
V
DDcore
to V
SScore
V
DDIO
to V
SSIO
Clock Frequency
Ambient Temperature
2.9
1.7
3.0
鈭?0
25
3.0
3.3
3.3
25
85
V
V
MHz
藲C
Units
+260藲C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3)
Symbol
MPL
I
OLL
I
OMS
I
OLH
I
B
I
OFF
V
IH
V
IL
V
HY
I
IN
I
IH
I
IL
V
OH
V
OL
I
OS
Logic Low Current (5X I
B
)
Mid Scale Current
Logic High Current (1X I
B
)
Current Bias
MPL Leakage Current
Input Voltage High Level
Input Voltage Low Level
Input Hysteresis
Input Current (includes I
OZ
)
Input Current High Level
Input Current Low Level
Output Voltage High Level
Output Voltage Low Level
Output Short-Circuit
Current
I
OH
= 鈭? mA
I
OL
= 2 mA
V
DDIO
= 3.3V
V
DDIO
= 1.7V
V
DDIO
= 3.3V
V
DDIO
= 1.7V
V
OUT
= 0V, V
DDIO
= 1.7 V
V
OUT
= 0V, V
DDIO
= 3.3 V
PD* = L (PowerDown mode)
V
DDIO
= 2.0V to 3.3V
V
DDIO
= 1.7V to
<
2.0V
V
DDIO
= 2.0V to 3.3V
V
DDIO
= 1.7V to
<
2.0V
V
DDIO
= 3.0V
V
DDIO
= 1.8V
LVCMOS IO Signals
LVCMOS Input Only Signals (i.e. Mode)
鈭?
鈭?
鈭?
0.8 V
DDIO
鈭?
0.7 V
DDIO
0.8 V
DDIO
鈭?.3
鈭?.3
500
300
0
0
0
2.8
1.6
0.08
0.12
鈭?
鈭?0
0.2 V
DDIO
+2
+1
+1
0.7 I
B
3.67 I
B
5.0 I
B
3.0 I
B
1.0 I
B
150
0
+2
V
DDIO
+0.3
0.3 V
DDIO
0.2 V
DDIO
1.3 I
B
6.33 I
B
碌A
碌A
碌A
碌A
碌A
Parameter
Conditions
Min
Typ
Max
Units
LVCMOS (1.7V to 3.3V Operation)
V
V
V
mV
mV
碌A
碌A
碌A
V
V
mA
mA
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