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LM2502SM Datasheet

  • LM2502SM

  • National Semiconductor [Mobile Pixel Link (MPL) Display Int...

  • NSC

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LM2502
Pin Descriptions
Pin Name
No.
of Pins
2
1
I/O, Type
Description
Master (SER)
MPL Data Line Driver/Receiver
MPL Clock Line Driver
MPL Ground - see Power/Ground Pins
Master/Slave* Input,
M/S* = H for Master
Power_Down* Input,
H = Active
L = Power Down Mode
Multi-function Input Zero (0):
If MODE = L (m68 mode), E input pin,
data is latched on E High-to-Low
transition or E may be static High and
Data is latched on CS* Low-to-High edge
If MODE = H (i80 mode), Read Enable
input pin, active low. Read data is driven
when both RD* and CS* are Low.
Multi-function Input One (1):
If Mode = L (m68 mode), Read/Write*
pin, Read High, Write* Low
If Mode = H (i80 mode), Write* enable
input pin, active Low. Write data is
latched on the Low-to-High transition of
either WR* or CS* (which ever occurs
first).
ChipSelect1* 鈥?Input
H = Ignored
L = Active
ChipSelect2* 鈥?Input
H = Ignored
L = Active
Address/Data 鈥?Input
H = Data
L = Address (Command)
Data Bus 鈥?Inputs/Outputs
INTR is asserted when the read data is
ready and de-asserted upon a second
CPU Read cycle.
Slave (DES)
MPL Data Receiver/Line Driver
MPL Clock Receiver
MPL Ground - see Power/Ground Pins
Master/Slave* Input
M/S* = L for Slave
Power_Down* Input,
H = Active
L = Power Down Mode
Multi-function Output Zero (0):
If MODE = L (m68 mode),
E output pin, static High.
If MODE = H (i80 mode),
Read Enable output pin, active Low.
MPL SERIAL BUS PINS
MD[1:0]
MC
V
SSA
M/S*
PD*
1
1
IO, MPL
IO, MPL
Ground
I,
LVCMOS
I,
LVCMOS
IO,
LVCMOS
CONFIGURATION/PARALLEL BUS PINS
MF0
(E or RD*)
1
MF1
(R/W* or
WR*)
1
IO,
LVCMOS
Multi-function Output One (1):
If Mode = L (m68 mode)
Read/Write* pin,
Read High, Write* Low
If Mode = H (i80 mode)
Write* enable output pin, active Low.
CS1*
1
IO,
LVCMOS
IO,
LVCMOS
IO,
LVCMOS
IO,
LVCMOS
O or I,
LVCMOS
ChipSelect1* 鈥?Output
H = Ignored
L = Active
ChipSelect2* 鈥?Output
H = Ignored
L = Active
Address/Data 鈥?Output
H = Data
L = Address (Command)
Data Bus 鈥?Outputs/Inputs
Clock Disable - CLKDIS*:
H = CLK output ON
L = CLK output LOW, allows for the
Slave clock output to be held static if not
used.
Clock Output (Frequency Reference) 鈥?/div>
no phase relationship to data 鈥?frequency
reference only.
Mode Input Pin
H = i80 Mode,
L = m68 Mode
Clock Divisor Configuration Input Pins 鈥?/div>
see
Table 10
CS2*
1
A/D (RS or
A0)
D[15:0]
INTR
or
CLKDIS*
1
16
1
CLK
1
IO,
LVCMOS
I,
LVCMOS
I,
LVCMOS
Clock Input
Mode
1
Mode Input Pin
H = i80 Mode,
L = m68 Mode
PLL Configuration Input Pins 鈥?see
Table
10
PLL_CON
[2:0]
3
www.national.com
4

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