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LFECP10E-3T100I Datasheet

  • LFECP10E-3T100I

  • Lattice Semiconductor [LatticeECP/EC Family Data Sheet]

  • LATTICE   LATTICE

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Lattice Semiconductor
Differential HSTL and SSTL
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-
able single-ended output classes (class I and class II) are supported in this mode.
BLVDS
The LatticeECP/EC devices support BLVDS standard. This standard is emulated using complementary LVCMOS
outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when
multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-1 is one
possible solution for bi-directional multi-point differential signals.
Figure 3-1. BLVDS Multi-point Output Example
Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential
2.5V
80
45-90 ohms
45-90 ohms
80
2.5V
80
2.5V
2.5V
80
+
-
80
...
-
+
80
80
+
-
-
2.5V
2.5V
2.5V
2.5V
Table 3-1. BLVDS DC Conditions
1
Over Recommended Operating Conditions
Typical
Parameter
Z
OUT
R
TLEFT
R
TRIGHT
V
OH
V
OL
V
OD
V
CM
I
DC
Description
Output impedance
Left end termination
Right end termination
Output high voltage
Output low voltage
Output differential voltage
Output common mode voltage
DC output current
Zo = 45
100
45
45
1.375
1.125
0.25
1.25
11.2
Zo = 90
100
90
90
1.48
1.02
0.46
1.25
10.2
Units
ohm
ohm
ohm
V
V
V
V
mA
1. For input buffer, see LVDS table.
3-8
+

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