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LFECP10E-3T100I Datasheet

  • LFECP10E-3T100I

  • Lattice Semiconductor [LatticeECP/EC Family Data Sheet]

  • 539.18KB

  • LATTICE   LATTICE

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Lattice Semiconductor
Figure 2-33. LatticeECP/EC Banks
GND
V
REF2(0)
GND
V
REF2(1)
V
CCIO0
V
REF1(0)
V
REF1(1)
V
CCIO1
Architecture
LatticeECP/EC Family Data Sheet
V
CCIO7
Bank 0
Bank 1
V
CCIO2
V
REF1(2)
V
REF2(2)
GND
V
CCIO3
Bank 7
V
REF1(7)
V
REF2(7)
GND
V
CCIO6
V
REF2(6)
GND
Bank 2
Bank 6
V
REF1(6)
V
REF1(3)
V
REF2(3)
GND
Bank 3
M
Bank 5
Bank 4
V
REF1(4)
V
REF2(4)
V
REF2(5)
V
REF1(5)
V
CCIO5
V
CCIO4
GND
Note: N and M are the maximum number of I/Os per bank.
LatticeECP/EC devices contain two types of sysIO buffer pairs.
1.
Top and Bottom sysIO Buffer Pair (Single-Ended Outputs Only)
The sysIO buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be
con鏗乬ured as a differential input.
The two pads in the pair are described as 鈥渢rue鈥?and 鈥渃omp鈥? where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
Only the I/Os on the top and bottom banks have PCI clamp.
2.
Left and Right sysIO Buffer Pair (Differential and Single-Ended Outputs)
The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-
enced input buffer can also be con鏗乬ured as a differential input. In these banks the two pads in the pair are
described as 鈥渢rue鈥?and 鈥渃omp鈥? where the true pad is associated with the positive side of the differential I/O,
and the comp (complementary) pad is associated with the negative side of the differential I/O.
Only the left and right banks have LVDS differential output drivers.
Supported Standards
The LatticeECP/EC sysIO buffer supports both single-ended and differential standards. Single-ended standards
can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2,
1.5, 1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually con鏗乬urable
2-29
GND

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