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LFECP10E-3T100I Datasheet

  • LFECP10E-3T100I

  • Lattice Semiconductor [LatticeECP/EC Family Data Sheet]

  • LATTICE   LATTICE

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Lattice Semiconductor
MULT sysDSP Element
Architecture
LatticeECP/EC Family Data Sheet
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-18 shows the MULT sysDSP element.
Figure 2-18. MULT sysDSP Element
Shift Register B In
Multiplicand
m
Shift Register A In
m
m
Multiplier
n
n
n
Output
Register
Input Data
Register A
m
Multiplier
Input Data
Register B
m
n
n
x
Pipeline
Register
m+n
(default)
m+n
Output
Signed
Input
Register
To
Multiplier
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Shift Register B Out
Shift Register A Out
MAC sysDSP Element
In this case the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-
put register is always enabled. The output register is used to store the accumulated value. A registered over鏗俹w
signal is also available. The over鏗俹w conditions are provided later in this document. Figure 2-19 shows the MAC
sysDSP element.
Figure 2-19. MAC sysDSP Element
Shift Register B In
Multiplicand
m
m
Input Data
Register A
m
Multiplier
Shift Register A In
m
Accumulator
n
Input Data
Register B
n
n
x
Output
Register
Multiplier
n
n
m+n+16 bits
(default)
m+n
(default)
m+n+16 bits
(default)
Output
n
SignedAB
Addn
Accumsload
Input
Register
Input
Register
Input
Register
Pipeline
Register
Pipeline
Register
Pipeline
Register
Overflow
Register
Pipeline
Register
To
Accumulator
To
Accumulator
To
Accumulator
Overflow
signal
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Shift Register B Out
Shift Register A Out
2-16

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