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LFECP10E-3T100I Datasheet

  • LFECP10E-3T100I

  • Lattice Semiconductor [LatticeECP/EC Family Data Sheet]

  • 539.18KB

  • LATTICE   LATTICE

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Lattice Semiconductor
Figure 2-16. Memory Core Reset
Memory Core
D
SET
Architecture
LatticeECP/EC Family Data Sheet
Q
Port A[17:0]
L
CLR
Output Data
Latches
D
SET
Q
Port B[17:0]
L
CLR
RSTA
RSTB
GSRN
Programmable Disable
For further information on sysMEM EBR block, please see the details of additional technical documentation at the
end of this data sheet.
sysDSP Block
The LatticeECP-DSP family provides a sysDSP block making it ideally suited for low cost, high performance Digital
Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response
(FIR) 鏗乴ters; Fast Fourier Transforms (FFT) functions, correlators, Reed-Solomon/Turbo/Convolution encoders and
decoders. These complex signal processing functions use similar building blocks such as multiply-adders and mul-
tiply-accumulators.
sysDSP Block Approach Compare to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with
鏗亁ed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by
higher clock speeds. The LatticeECP, on the other hand, has many DSP blocks that support different data-widths.
This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the
DSP performance vs. area by choosing appropriate level of parallelism. Figure 2-17 compares the serial and the
parallel implementations.
2-14

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