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LFECP10E-3T100I Datasheet

  • LFECP10E-3T100I

  • Lattice Semiconductor [LatticeECP/EC Family Data Sheet]

  • 539.18KB

  • LATTICE   LATTICE

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Lattice Semiconductor
Memory Cascading
Architecture
LatticeECP/EC Family Data Sheet
Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on speci鏗乧 design inputs.
Single, Dual and Pseudo-Dual Port Modes
Figure 2-15 shows the four basic memory con鏗乬urations and their input/output names. In all the sysMEM RAM
modes the input data and address for the ports are registered at the input of the memory array. The output data of
the memory is optionally registered at the output.
Figure 2-15. sysMEM EBR Primitives
ADA[12:0]
DIA[17:0]
CLKA
CEA
DO[35:0]
RSTA
WEA
CSA[2:0]
DOA[17:0]
ADB[12:0]
DIB[17:0]
CEB
CLKB
RSTB
WEB
CSB[2:0]
DOB[17:0]
AD[12:0]
DI[35:0]
CLK
CE
RST
WE
CS[2:0]
EBR
EBR
Single Port RAM
True Dual Port RAM
AD[12:0]
CLK
CE
RST
CS[2:0]
EBR
ADW[12:0]
DI[35:0]
CLKW
CEW
DO[35:0]
WE
RST
CS[2:0]
ADR[12:0]
EBR
DO[35:0]
CER
CLKR
ROM
Pseudo-Dual Port RAM
The EBR memory supports three forms of write behavior for single port or dual port operation:
1.
Normal
鈥?data on the output appears only during read cycle. During a write cycle, the data (at the current
address) does not appear on the output.
2.
Write Through
鈥?a copy of the input data appears at the output of the same port, during a write cycle.
3.
Read-Before-Write
鈥?when new data is being written, the old content of the address appears at the output.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated
resets for both ports are as shown in Figure 2-16.
2-13

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