CS8405A
SWITCHING CHARACTERISTICS - CONTROL PORT - Two-Wire MODE
(Note 13, T
A
= 25 擄C for suffixes 鈥楥S鈥?&鈥機(jī)Z鈥? T
A
= -40 to 85擄C for 鈥業(yè)S鈥?& 鈥業(yè)Z鈥?; VD+ = VL+ = 5V 鹵10%, Inputs: Logic 0
= 0V, Logic 1 = VL+; C
L
= 20pF)
Parameter
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time to SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
(Note 14)
Symbol
f
scl
t
buf
t
hdst
t
low
t
high
t
sust
t
hdd
t
sud
t
r
t
f
t
susp
Min
-
4.7
4.0
4.7
4.0
4.7
0
250
-
-
4.7
Typ
-
-
-
-
-
-
-
-
-
-
-
Max
100
-
-
-
-
-
-
-
25
25
-
Units
kHz
碌s
碌s
碌s
碌s
碌s
碌s
ns
ns
ns
碌s
Notes: 13. Two-Wire Mode is compatible with the I
2
C
廬
protocol and is supported only at 5V mode.
14. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Stop
SDA
t buf
SCL
Start
Repeated
Start
Stop
t hdst
t high
t
hdst
tf
t susp
t
low
t
hdd
t sud
t sust
tr
Figure 4. Two-Wire Mode timing
8
DS469PP4