最新免费av在线观看,亚洲综合一区成人在线,中文字幕精品无码一区二区三区,中文人妻av高清一区二区,中文字幕乱偷无码av先锋

CS493112-CL Datasheet

  • CS493112-CL

  • Multi-Standard Audio Decoder Family

  • CIRRUS

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書(shū)

PDF預(yù)覽

CS49300 Family DSP
B Value
Data Format
8
PCM - Left Justified 24-bit
Multichannel PCM (6 Channel)
- Left Justified 20-bit
(for Post-Processing Codes that can
accept 6 channels on one line like
THX Surround EX application code)
82
PCM - Left Justified 24-bit
Multichannel PCM (2 Channel)
- Left Justified 20-bit
(used only by special post-processing
application codes)
84
PCM - Left Justified 24-bit
Multichannel PCM (4 Channel)
- Left Justified 20-bit
(used only by special post-processing
application codes)
Hex
Message
0x800217
0x8080FF
0x80021A
0x8080FF
0x800117
0x003CC0
0x80011A
0x0018C0
0x800217
0x8080FF
0x80021A
0x8080FF
0x800117
0x0014C0
0x80011A
0x0018C0
0x800217
0x8080FF
0x80021A
0x8080FF
0x800117
0x0028C0
0x80011A
0x0018C0
FIFO Size & Blocksize (no
default - only applicable to
D Value
parallel delivery modes)
1
Compressed FIFO B Size -
6kbyte
Blocksize - up to 2kbyte
2
PCM FIFO C Size - 6kbyte
Blocksize - up to 2kbyte
Hex
Message
0x800014
0x280D00
0x800014
0x820300
Table 21. Input FIFO Setup Configuration
(Input Parameter D)
per sub-frame. The DSP always uses 24-bit
resolution for PCM input. Systems having less
than 24-bit resolution will not have a problem
as the extra bits taken by the DSP will be under
the noise floor of the input signal for left
justified and I
2
S formats. For compressed
input, data is always taken in 16 bit word
lengths.
2) If the clocks to the audio ports are known to be
corrupted, such as when a S/PDIF receiver goes
out of lock, the DSP should undergo an
application restart (if applicable), soft reset or
hard reset. All three actions will result in the
input FIFO being reset. Failure to do so
may
result in corrupted data being latched into the
input FIFO and may result in corrupted data
being heard on the outputs. This is not an issue
when compressed data is being delivered, as it
has sync words embedded in the stream which
the DSP can lock to, but only when PCM data
is being delivered. Certain application codes
that are capable of processing PCM may now
have a special feature called 鈥淧CM
Robustness鈥?which does alleviate the above
problem, however you should still follow the
above recommendation.
Table 19. Input Data Format Configuration
(Input Parameter B) (Continued)
SCLK Polarity (Both CDI &
Hex
C Value
DAI Port)
Message
0
Data Clocked in on Rising
0x800217
(default) Edge
0xFFFFDF
0x80021A
0xFFFFDF
1
Data Clocked in on Falling
0x800117
Edge
0x000020
0x80011A
0x000020
Table 20. Input SCLK Polarity Configuration
(Input Parameter C)
11.2.1. Input Configuration Considerations
1) 24-bit PCM input requires at least 24 SCLKS
DS339PP4
75

CS493112-CL相關(guān)型號(hào)PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號(hào)推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn)，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見(jiàn)一經(jīng)采納，將有感恩紅包奉上哦！