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CS493112-CL Datasheet

  • CS493112-CL

  • Multi-Standard Audio Decoder Family

  • CIRRUS

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CS49300 Family DSP
RESET(LOW)
(NOTE 1)
ABOOT(LOW)
RESET(HIGH)
(NOTE 2)
RELEASE ABOOT
WAIT 200 MS
(NOTE 3)
READ_*(VARIABLE)
(NOTE 4)
CORRECT VALUE?
Y
N
WAIT 5 MS
AUTOBOOT COMPLETE
WRITE_*(HW_CONFIG_MSG,
HW_MSG_SIZE)
(NOTE 4)
Notes: 1. RESET must be held LOWT
rstl
.
2. The RD and WR pins must be configured to select a
serial communication mode as defined in the
CS493XX Datasheet. The setup (T
rstsu
) and hold
(T
rsthld
) times must be observed for the RD, WR, and
AUTOBOOT pins.
3. INTREQ should be ignored during this period. 200 ms
is typical but this time is application code specific and
may be higher. Wait times should be verified by the
designer.
4. The READ_* and WRITE_* functions are
placeholders for the READ_I2C/READ_SPI and
WRITE_I2C/WRITE_SPI functions defined in
Section
6.1, 鈥淪erial Communication鈥?on page 33.
WRITE_*(SW_CONFIG_MSG,
SW_MSG_SIZE)
(NOTE 4)
WRITE_*(KICKSTART,
MSG_SIZE)
(NOTE 4)
Figure 36. Autoboot Sequence
58
DS339PP4

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