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CS493112-CL Datasheet

  • CS493112-CL

  • Multi-Standard Audio Decoder Family

  • CIRRUS

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CS49300 Family DSP
RESET(LOW)
(NOTE 1)
RESET(HIGH)
(NOTE 2)
WAIT
500
碌s
WRITE_*(DOWNLOAD_
BOOT, MSG_SIZE)
READ HOSTCTL
REGISTER
N
HOUTRDY LOW?
Y
READ_*(MESSAGE)
TIMEOUT AFTER
20MS
(NOTE 3)
Notes: 1. RESET must be held LOW for
t
rstl
.
2. It should be noted that mode
pins are used to configure the
CS493XX serial communication
mode. These mode pins are
latched internally on the rising
edge of reset. The pins can be
set dynamically by a
microprocessor or can be
statically pulled HIGH or LOW. If
these pins are driven
dynamically, setup and hold
times must be satisfied as stated
in the
CS493XX Data Sheet.
More information about the
function of the mode pins can be
found in the CS493XX Data
Sheet and in
Section 6, 鈥淐ontrol鈥?/span>
on page 32.
3. Time-out values reflect worst
case response time for the
CS493XX. The values shown
may be used for the host鈥檚 time-
out control loop.
4. 5 ms is typical but this time is
application code specific and
may be as high as 10 ms. Wait
times should be verified by the
designer.
MESSAGE ==
BOOTSTART?
Y
WRITE_*(.LD FILE,
DOWNLOAD FILE SIZE)
N
EXIT(ERROR)
READ HOSTCTL
REGISTER
N
HOUTRDY LOW?
Y
READ_*(MESSAGE)
TIMEOUT AFTER
20MS
(NOTE 3)
MESSAGE ==
BOOT_SUCCESS?
Y
WRITE_*(BOOT_
SUCCESS_RECEIVED,
MSG-SIZE)
N
EXIT(ERROR)
5. Hardware configuration
messages are covered in
Section 6, 鈥淐ontrol鈥?on page 32.
Application configuration
messages are covered in each
application code user鈥檚 manual.
WAIT 5 MS
(NOTE 4)
DOWNLOAD COMPLETE
WRITE_*(HW_CONFIG_MSG,
HW_MSG_SIZE)
(NOTE 5)
WRITE_*(SW_CONFIG_MSG,
SW_MSG_SIZE)
(NOTE 5)
WRITE_*(KICKSTART,
MSG_SIZE)
(NOTE 5)
Figure 34. Typical Parallel Boot and Download Procedure
54
DS339PP4

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