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CS4929 Datasheet

  • CS4929

  • Multi-Channel Digital Audio Decoders

  • CIRRUS

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CS4923/4/5/6/7/8/9
Following the address byte the host must clock out
an acknowledge from the part.
After the address byte, the host should clock out data
from the device one byte at a time until INTREQ is
no longer low. The host shifts data using the rising
edge of SCCLK. The data is valid on the rising edge
of SCCLK and transitions on the falling edge. After
each byte the host must send an acknowledge (ACK)
to the CS492X. While reading from the CS492X, an
acknowledge is defined as SCDIO being driven low
by the host for one SCCLK period after each byte. In
I
2
C mode, the INTREQ pin is deasserted
immediately following the rising edge of the last
data bit of the current byte being transferred if there
is no more data to be read. The INTREQ pin is
guaranteed to stay deasserted (high) until the rising
edge of SCCLK for the acknowledge bit.
For a more thorough look at I communication
and critical additional information on INTREQ
behavior reference the CS4923/4/5/6/7/8/9
Hardware User鈥檚 Guide.
2
C
The external memory interface is implemented on
the CS4923/4/5/6/7/8/9 with the following signals:
EMAD[7:0], EXTMEM and EMOE. Table 9 shows
the pin name, pin description and pin number of each
signal on the CS4923/4/5/6/7/8/9. EMAD[7:0] serve
as a multiplexed address and data bus. EMOE is an
active-low external-memory data output enable as
well as the address latch strobe. EXTMEM serves as
the active low chip select output. Figure 21 illustrates
one possible external memory architecture for the
CS4923/4/5/6/7/8/9. Figure 22 shows the functional
timing of a run-time memory access .
Pin Name
/EMOE
Pin Description
* External Memory Output
Enable & Address Latch
Strobe
* External Memory Write
Strobe
External Memory Select
Address and Data Bit 7
Address and Data Bit 6
Address and Data Bit 5
Address and Data Bit 4
Address and Data Bit 3
Address and Data Bit 2
Address and Data Bit 1
Address and Data Bit 0
Pin
Number
5
/EMWR
/EXTMEM
EMAD7
EMAD6
EMAD5
EMAD4
EMAD3
EMAD2
EMAD1
EMAD0
4
21
8
9
10
11
14
15
16
17
6.5 External Memory
If using one of the serial modes, i.e. SPI or I
2
C, the
system designer has the option of using external
memory. The external memory interface is not
compatible with the parallel modes since there are
shared pins that are needed by each mode. If using
the CS4926 or CS4928 for DTS decode, external
memory is required for external DTS tables.
The external memory interface was designed
primarily for two purposes: 1) Autoboot and/or 2)
real time external data access. The hardware
implementation for either mode can be the same but
the ROM access time requirements may differ. The
CS4923/4/5/6/7/8/9 Hardware User鈥檚 Guide should
be referenced for more information including
memory paging options to support both autoboot and
real time access as well as ROM speed requirements.
* - These pins must be configured appropriately to select a
serial host communication mode for the CS4923/4/5/6/7/8/9
at the rising edge of RESET
Table 9. Memory Interface Pins
The external memory address is capable of addressing
between 64 kilobytes and 16 megabytes through a 16
to 24 bit addressing scheme. The address comes from
the DSP writing two or three initial bytes of address
consecutively on EMAD[7:0]. Each byte of address is
externally latched with the rising edge of EMOE while
EXTMEM is high. After the 2 or 3-byte address is
latched externally, the CS4923/4/5/6/7/8/9 then drives
EXTMEM and EMOE low simultaneously to select
the external memory. During this time the data is read
by the CS492X.
DS262F2
41

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