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CS4925 Datasheet

  • CS4925

  • Multi-Channel Digital Audio Decoders

  • CIRRUS

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CS4923/4/5/6/7/8/9
SWITCHING CHARACTERISTICS鈥擠IGITAL AUDIO OUTPUT
(T
A
= 25
擄C;
VA, VD = 3.3 V
鹵5%;
measurements performed under static conditions.)
Parameter
MCLK period
MCLK duty cycle
SCLK period for Master or Slave mode
SCLK duty cycle for Master or Slave mode
Master Mode
(Note 24)
(Note 24)
(Note 25)
(Note 25)
(Note 25,26)
T
sdmi
T
sdmo
T
lrds
T
adsm
T
stlr
T
lrts
T
adss
10
10
鈥?
15
10
10
10
-
-
15
ns
ns
ns
ns
ns
ns
ns
T
sclk
Symbol
T
mclk
Min
40
40
40
45
Max
-
60
-
55
Unit
ns
%
ns
%
SCLK delay from MCLK rising edge, MCLK as an input
SCLK delay from MCLK rising edge, MCLK as an output
LRCLK delay from SCLK transition
AUDATA2鈥? delay from SCLK transition
Slave Mode
(Note 27)
(Note 27)
(Note 28)
Time from active edge of SCLKN1(2) to LRCLKN1(2) transition
Time from LRCLKN1(2) transition to SCLKN1(2) active edge
AUDATA2鈥? delay from SCLK transition
(Note 27,29)
Notes: 24. MCLK can be an input or an output. These specifications apply for both cases.
25. Master mode timing specifications are characterized, not production tested.
26. Master mode is defined as the CS4923 driving both SCLK and LRCLK. When MCLK is an input, it is
divided to produce SCLK and LRCLK.
27. This timing parameter is defined from the non-active edge of SCLK. The active edge of SCLK is the
point at which the data is valid.
28. Slave mode is defined as SCLK and LRCLK being driven by an external source.
29. This specification is characterized, not production tested.
18
DS262F2

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