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CS4924 Datasheet

  • CS4924

  • Multi-Channel Digital Audio Decoders

  • CIRRUS

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CS4923/4/5/6/7/8/9
SWITCHING CHARACTERISTICS鈥擬OTOROLA
廬
HOST MODE
(T
A
= 25
擄C;
VA, VD = 3.3 V
鹵5%;
Inputs: Logic 0 = DGND, Logic 1 = VD, C
L
= 20 pF)
Parameter
Address setup before CS and DS low
Address hold time after CS and DS low
Delay between DS then CS low or CS then DS low
Data valid after CS and DS low with R/W high
CS and DS low for read
Data hold time after CS or DS high after read
Data high-Z after CS or DS high low after read
CS or DS high to CS and DS low for next read
CS or DS high to CS and DS low for next write
Delay between DS then CS low or CS then DS low
Data setup before CS or DS high
CS and DS low for write
R/W setup before CS or DS low
R/W hold time after CS or DS high
Data hold after CS or DS high
CS or DS high to CS and DS low with R/W high for next read
(Note 3)
CS or DS high to CS and DS low for next write
(Note 3)
(Note 3)
(Note 4)
(Note 3)
(Note 3)
(Note 3)
Symbol
T
mas
T
mah
T
mcdr
T
mdd
T
mrpw
T
mdhr
T
mdis
T
mrd
T
mrdtw
T
mcdw
T
mdsu
T
mwpw
T
mrwsu
T
mrwhld
T
mdhw
T
mwtrd
T
mwd
Min
5
5
0
-
DCLK + 10
5
-
2*DCLK + 10
2*DCLK + 10
0
20
DCLK + 10
5
5
5
2*DCLK + 10
2*DCLK + 10
Max
-
-
鈭?/div>
20
-
-
15
-
-
鈭?/div>
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 3. Certain timing parameters are normalized to the DSP clock, DCLK, in nanoseconds. The DSP clock can
be defined as follows:
External CLKIN Mode:
DCLK == CLKIN/3 before and during boot
DCLK == CLKIN after boot
Internal Clock Mode:
DCLK == 10MHz before and during boot, i.e. DCLK == 100ns
DCLK == 60 MHz after boot, i.e. DCLK == 16.7ns (this speed may depend on CLKIN, please see
CS4923/4/5/6/7/8/9 Hardware Users Guide for more information)
4. This specification is characterized but not production tested.
10
DS262F2

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