DDR SDRAM 1Gb M-die (x4, x8)
AC Timming Parameters & Specifications
Parameter
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/
Data strobe edge to ouput data
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup
DQS falling edge from CK rising-
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup
Address and Control Input hold
Address and Control Input setup
Address and Control Input hold
Data-out high impedence time from
CK/CK
Data-out low impedence time from
CK/CK
Output Slew Rate Matching
CL=2.0
CL=2.5
DDR SDRAM
A2
(DDR266@CL=2.0)
Min
65
120
Symbol
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
tCCD
tCK
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tDSC
tIS
tIH
tIS
tIH
tHZ
tLZ
tSLMR
B3
(DDR333@CL=2.5))
Min
60
120
42
18
18
12
15
1
1
7.5
6
0.45
0.45
-0.6
-0.7
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.75
0.75
0.8
0.8
+0.7
-0.7
0.67
+0.7
1.5
1.1
12
12
0.55
0.55
+0.6
+0.7
0.45
1.1
0.6
1.25
70K
B0
(DDR266@CL=2.5))
Min
65
120
Unit
ns
ns
Note
Max
Max
Max
45
20
20
15
15
1
1
7.5
7.5
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.9
1.0
1.0
120K
45
20
20
15
15
1
1
120K
ns
ns
ns
ns
ns
tCK
tCK
12
12
0.55
0.55
+0.75
+0.75
0.5
1.1
0.6
1.25
10
7.5
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
12
12
0.55
0.55
+0.75
+0.75
0.5
1.1
0.6
1.25
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
tCK
3
12
1.1
0.9
0.9
0.9
1.0
1.0
1.1
tCK
ns
ns
ns
ns
i,5.7~9
i,5.7~9
i, 6~9
i, 6~9
1
1
+0.75
-0.75
0.67
+0.75
1.5
-0.75
0.67
+0.75
+0.75
1.5
ns
ns
Revision 1.0 October, 2004