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CS8416-CS Datasheet

  • CS8416-CS

  • Cirrus Logic [192 kHZ DIGITAL AUDIO INTERFACE RECEIVER]

  • CIRRUS

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CS8416
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(T
A
= 25 擄C for suffixes 鈥楥S鈥?&鈥機(jī)Z鈥? T
A
= -40 to 85擄C for 鈥業(yè)S鈥?& 鈥業(yè)Z鈥?; VA+ = VD+ = 3.3 V 鹵 5%, VL+ = 3.135 to 5.5V,
Inputs: Logic 0 = 0 V, Logic 1 = VL+; C
L
= 20 pF)
Parameter
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note
11)
(Note
11)
(Note
10)
(Note
9)
Symbol
f
sck
t
csh
t
css
t
scl
t
sch
t
dsu
t
dh
t
pd
t
r1
t
f1
t
r2
t
r2
Min
0
1.0
20
66
66
40
15
-
-
-
-
-
Max
6.0
-
-
-
-
-
-
50
25
25
100
100
Unit
MHz
碌s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 9. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is
dictated by the timing requirements necessary to access the Channel Status memory. Access to the
control register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate
is 32 kHz, so choosing CCLK to be less than or equal to 4.1 MHz should be safe for all possible
conditions.
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For f
sck
<1 MHz.
CS
t css
CCLK
t r2
CDIN
t dsu
t dh
t f2
t scl
t sch
t csh
t pd
CDOUT
Figure 3. SPI Mode Timing
8
DS578PP2

CS8416-CS PDF文件相關(guān)型號(hào)

CS8416-CZ

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