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CS8416-CS Datasheet

  • CS8416-CS

  • Cirrus Logic [192 kHZ DIGITAL AUDIO INTERFACE RECEIVER]

  • 764.03KB

  • CIRRUS

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CS8416
12 APPLICATIONS
12.1
Reset, Power Down and Start-up
When RST is low, the CS8416 enters a low power
mode and all internal states are reset, including the
control port and registers, and the outputs are mut-
ed. In Software Mode, when RST is high, the con-
trol port becomes operational and the desired
settings should be loaded into the control registers.
Writing a 1 to the RUN bit will then cause the part
to leave the low power state and begin operation.
After the PLL has settled, the serial audio outputs
will be enabled.
Some options within the CS8416 are controlled by
a start-up mechanism. During the reset state, some
of the pins are reconfigured internally to be inputs.
Immediately upon exiting the reset state, the level
of these pins is sensed. The pins are then switched
to be outputs. This mechanism allows output pins
to be used to set alternative modes in the CS8416
by connecting a 47K resistor to between the pin and
either VL+ (HI) or DGND (LO). For each mode,
every start-up option select pin MUST have an ex-
ternal pull-up or pull-down resistor. In software
mode, the only start-up option pins are GPO2,
which are used to set a chip address bit for the con-
trol port in I
2
C mode, and SDOUT, which selects
between Hardware and Software Modes. The hard-
ware mode uses many start-up options, which are
detailed in the hardware definition section at the
end of this data sheet.
CS8416. This is useful when other CS84XX
family members are resident in the same system,
allowing common software modules.
The CS8416 4-bit revision code is also available.
This allows the software driver for the CS8416 to
identify which revision of the device is in a
particular system, and modify its behavior
accordingly. To allow for future revisions, it is
strongly recommend that the revision code is read
into a variable area within the microcontroller, and
used wherever appropriate as revision details
become known.
12.3
Power Supply, Grounding, and PCB
layout
For most applications, the CS8416 can be operated
from a single +3.3 V supply, following normal
supply decoupling practices. (See
Figure 5
and
Figure 6).
For applications where the recovered
input clock, output on the RMCK pin, is required
to be low jitter, then use a separate, quiet, analog
+3.3 V supply for VA+, decoupled to AGND. In
addition, a separate region of analog ground plane
around the FILT, AGND, VA+, RXP0-7 and RXN
pins is recommended. VL+ sets the level for the
digital
inputs and outputs, as well as the
AES/SPDIF inputs.
Extensive use of power and ground planes, ground
plane fill in unused areas and surface mount decou-
pling capacitors are recommended. Decoupling ca-
pacitors should be mounted on the same side of the
board as the CS8416 to minimize inductance ef-
fects, and all decoupling capacitors should be as
close to the CS8416 as possible. Refer to AN159
for examples of proper techniques.
12.2
ID Code and Revision Code
The CS8416 has a register that contains a 4-bit
code to indicate that the addressed device is a
42
DS578PP2

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