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CS8416-CS Datasheet

  • CS8416-CS

  • Cirrus Logic [192 kHZ DIGITAL AUDIO INTERFACE RECEIVER]

  • CIRRUS

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CS8416
11 PIN DESCRIPTION - HARDWARE MODE
RXP3
RXP2
RXP1
RXP0
RXN
VA+
AGND
FILT
RST
RXSEL1
RXSEL0
TXSEL1
TXSEL0
NV/RERR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OLRCK
OSCLK
SDOUT
OMCK
RMCK
VD+
DGND
VL+
TX
C
U
RCBL
96 KHZ
AUDIO
RXP[3:0]
1
2
3
4
5
Additional AES3/SPDIF Receiver Port
(
Input
) - Single-ended receiver inputs carrying AES3 or
S/PDIF digital data. These inputs comprise the 4:2 S/PDIF Input Multiplexer. The select line control is
the RXSEL[1:0] pins. Please note that any unused inputs can be left floating. See Appendix A for rec-
ommended input circuits.
RXN
VD+
VA+
VL+
DGND
AGND
RX_SEL0
RX_SEL1
TX_SEL0
TX_SEL1
FILT
AES/SPDIF Input -
Used along with RXP[X] to form an AES3 differential input. In single-ended
operation this should be capacitively coupled to ground
.
Positive Digital Power
鈥?3.3 V
Positive Analog Power 鈥?/div>
3.3 V
Positive Interface Power 鈥?/div>
3.3 V 鈥?5.0 V
Digital/Interface Ground
Analog Ground
Receiver_MUX Selector
(Input)
- used to select which pin, RXP[3:0], is used for the receiver
23
6
21
22
7
10
11
12
13
8
input.
TX Pin MUX SELECTION(Input)
- used to select which pin, RXP[3:0], is used for the TX pin
output.
PLL Filter Pin 鈥?/div>
A RC network should be connected from this pin to AGND. For best PLL jitter
performance, this pin should be returned directly to the AGND pin
RESET(Input) 鈥?/div>
active low input . Resets CS8416 to default state, configuration pins are read on the
rising edge of this pin
Non-Validity Receiver Error/Receiver Error
(output)
RST
9
NV/RERR
14
38
DS578PP2

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CS8416-CZ

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