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CS8416-CS Datasheet

  • CS8416-CS

  • Cirrus Logic [192 kHZ DIGITAL AUDIO INTERFACE RECEIVER]

  • 764.03KB

  • CIRRUS

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CS8416
8.13
7
0
Interrupt 1 Status (0Dh)
6
PCCH
5
OSLIP
4
DETC
3
CCH
2
RERR
1
QCH
0
FCH
For all bits in this register, a 鈥?鈥?means the associated interrupt condition has occurred at least once
since the register was last read. A 鈥?鈥?means the associated interrupt condition has NOT occurred
since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode
is set to level and the interrupt source is still true. Status bits that are masked off in the associated
mask register will always be 鈥?鈥?in this register.
PCCH 鈥?PC burst preamble change.
Indicates that the PC byte has changed from its previous value. The user has TBD frames to read
new value before it can potentially be overwritten again. If the IEC61937 bit in the Format Detect Sta-
tus register goes high, it will cause a PCCH interrupt even if the PC byte hasn鈥檛 changed since the last
time the IEC61937 bit went high.
OSLIP - Serial audio output port data slip interrupt
When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port data
source, This bit will go high every time a data sample is dropped or repeated.
DETC - D to E C-buffer transfer interrupt.
The source for this bit is true during the D to E buffer transfer in the C bit buffer management process.
C_CHANGE -Indicates that the current 10 bytes of channel status is different from the previous
10 bytes. (5 bytes per channel)
RERR - A receiver error has occurred.
The Receiver Error register may be read to determine the nature of the error which caused the inter-
rupt.
QCH 鈥?A new block of Q-subcode is available for reading. The data must be read within 588 AES3
frames after the interrupt occurs to avoid corruption of the data by the next block.
FCH 鈥?/div>
Format Change: Goes high when the PCM, IEC61937, DTS_LD, DTS_CD, or DGTL_SIL
bits in the Format Detect Status register transition from 0 to 1. When these bits in the Format
Detect Status register transition from 1 to 0, an interrupt will not be generated.
8.14
Q-Channel Subcode (0Eh - 17h)
7
6
5
4
3
2
1
0
CONTROL
CONTROL
CONTROL
CONTROL
ADDRESS
ADDRESS
ADDRESS
ADDRESS
TRACK
TRACK
TRACK
TRACK
TRACK
TRACK
TRACK
TRACK
INDEX
INDEX
INDEX
INDEX
INDEX
INDEX
INDEX
INDEX
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
SECOND
SECOND
SECOND
SECOND
SECOND
SECOND
SECOND
SECOND
FRAME
FRAME
FRAME
FRAME
FRAME
FRAME
FRAME
FRAME
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE
ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND
ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME
Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus bit 7 of address 0Eh is Q[0]
while bit 0 of address 0Eh is Q[7]. Similarly bit 0 of address 17h corresponds to Q[79].
32
DS578PP2

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