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CS8416-CS Datasheet

  • CS8416-CS

  • Cirrus Logic [192 kHZ DIGITAL AUDIO INTERFACE RECEIVER]

  • 764.03KB

  • CIRRUS

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CS8416
4 SERIAL AUDIO OUTPUT PORT
A 3-wire serial audio output port is provided. The
port can be adjusted to suit the attached device set-
ting the control registers. The following parameters
are adjustable: master or slave, serial clock fre-
quency, audio data resolution, left or right justifica-
tion of the data relative to left/right clock, optional
one-bit cell delay of the first data bit, the polarity of
the bit clock, and the polarity of the left/right clock.
By setting the appropriate control bits, many for-
mats are possible.
Figure 8
shows a selection of common output for-
mats, along with the control bit settings. A special
AES3 direct output format is included, which al-
lows the serial output port access to the V, U, and
C bits embedded in the serial audio data stream.
The P bit, which would normally be a parity bit, is
replaced by a Z bit, which is used to indicate the
start of each block. The received channel status
block start signal is also available as the RCBL pin
in hardware mode and through a GPO pin in soft-
ware mode.
In master mode, the left/right clock (OLRCK) and
the serial bit clock (OSCLK) are outputs, derived
from the recovered RMCK clock. In slave mode,
OLRCK and OSCLK are inputs. OLRCK is nor-
mally synchronous to the appropriate master clock,
but OSCLK can be asynchronous and discontinu-
ous if required. By appropriate phasing of OLRCK
and control of the serial clocks, multiple CS8416鈥檚
can share one serial port. OLRCK should be con-
tinuous, but the duty cycle can be less than the
specified typical value of 50% if enough serial
clocks are present in each phase to clock all the data
bits. When in slave mode, the serial audio output
port cannot be set for right-justified data. The
CS8416 allows immediate mute of the serial audio
output port audio data by the MUTESAO bit of
Control Register 1.
4.1
Slip/Repeat Behavior
When using the serial audio output port in slave
mode with an OLRCK input that is asynchronous
to the incoming AES3 data, the interrupt bit OSLIP
(bit 5 in the Interrupt 1 Status register, 0Dh) is pro-
vided to indicate when repeated or dropped sam-
ples occur. Refer to
Figure 7
for a AES3 data
format diagram.
When the serial output port is configured as slave,
depending on the relative frequency of OLRCK to
the input AES3 data (Z/X) preamble frequency, the
data will be slipped or repeated at the output of the
CS8416.
After a fixed delay from the Z/X preamble (a few
periods of the internal clock, which is running at
256Fs), the circuit will look back in time until the
previous Z/X preamble:
1) If during that time, the internal data buffer was
not updated, then a slip has occurred. Data from
the previous frame will be output and OSLIP
will be set to 1. Due to the OSLIP bit being
鈥渟ticky,鈥?it will remain 1 until the register is
read. It will then be reset until another slip/re-
peat condition occurs.
2) If during that time the internal data buffer did
not update between two positive or negative
edges (depending on OLRPOL) of OLRCK,
then a repeat has occurred. In this case the buff-
er data was updated twice, so the part has lost
one frame of data. This event will also trigger
OSLIP to be set to 1. Due to the OSLIP bit be-
ing 鈥渟ticky,鈥?it will remain 1 until the register is
read. It will then be reset until another slip/re-
peat condition occurs.
3) If during that time, it did see a positive edge on
OLRCK (or negative edge if the SOLRPOL is
set to 1) then no slip or repeat has happened.
Due to the OSLIP bit being 鈥渟ticky,鈥?it will re-
main in its previous state until either the regis-
ter is read or a slip/repeat condition occurs.
DS578PP2
13

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