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CS8415A-CS Datasheet

  • CS8415A-CS

  • Cirrus Logic [96 kHz DIGITAL AUDIO INTERFACE RECEIVER]

  • CIRRUS

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CS8415A
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL+; C
L
= 20 pF)
Parameter
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 14)
(Note 14)
(Note 13)
(Note 12)
Symbol
f
sck
t
csh
t
css
t
scl
t
sch
t
dsu
t
dh
t
pd
t
r1
t
f1
t
r2
t
f2
Min
0
1.0
20
66
66
40
15
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
Max
6.0
-
-
-
-
-
-
50
25
25
100
100
Units
MHz
碌s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 12. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is
dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum
allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should
be safe for all possible conditions.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For f
sck
<1 MHz.
CS
t css
CCLK
t r2
CDIN
t dsu
t dh
t f2
t scl
t sch
t csh
t pd
CDOUT
Figure 3. SPI Mode Timing
8

CS8415A-CS PDF文件相關(guān)型號(hào)

CS8415A-CZ,CS8415A-IZ

CS8415A-CS 產(chǎn)品屬性

  • Cirrus Logic

  • 音頻 DSP

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