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CS8415A-CS Datasheet

  • CS8415A-CS

  • Cirrus Logic [96 kHz DIGITAL AUDIO INTERFACE RECEIVER]

  • CIRRUS

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CS8415A
15.2.2 Serial Copy Management System
(SCMS)
In software mode, the CS8415A allows read ac-
cess to all the channel status bits. For consumer
mode SCMS compliance, the host microcontroller
needs to read and interpret the Category Code,
Copy bit and L bit appropriately.
In hardware mode, the SCMS protocol can be fol-
lowed by either using the COPY and ORIG output
pins, or by using the C bit serial output pin. These
options are documented in the hardware mode
section of this data sheet.
worth of information in 1 byte's worth of access
time. If the control port's autoincrement addressing
is used in combination with this mode, multi-byte
accesses such as full-block reads can be done es-
pecially efficiently.
15.2.3.2 Two Byte mode
There are those applications in which the A and B
channel status blocks will not be the same, and the
user is interested in accessing both blocks. In
these situations, two byte mode should be used to
access the E buffer.
In this mode, a read will cause the CS8415A to out-
put two bytes from its control port. The first byte out
will represent the A channel status data, and the
2nd byte will represent the B channel status data.
15.2.3 Channel Status Data E Buffer
Access
The E buffer is organized as 24 x 16-bit words. For
each word the MS Byte is the A channel data, and
the LS Byte is the B channel data (see Figure 15).
There are two methods of accessing this memory,
known as one byte mode and two byte mode. The
desired mode is selected by setting a control regis-
ter bit.
15.3
AES3 User (U) Bit Management
15.2.3.1 One Byte mode
In many applications, the channel status blocks for
the A and B channels will be identical. In this situ-
ation, if the user reads a byte from one of the chan-
nel's blocks, the corresponding byte for the other
channel will be the same. One byte mode takes ad-
vantage of the often identical nature of A and B
channel status data. When reading data in one
byte mode, a single byte is returned, which can be
from channel A or B data, depending on a register
control bit.
One byte mode saves the user substantial control
port access time, as it effectively accesses 2 bytes
Entire blocks of U data are buffered using a cas-
cade of 2 block-sized RAMs to perform the buffer-
ing. The user has access to the second of these
buffers, denoted the E buffer, through the control
port. The U buffer access only operates in two byte
mode, since there is no concept of A and B blocks
for user data. The arrangement of the data is as fol-
lowings:
Bit15[A7]Bit14[B7]Bit13[A6]Bit12[B6]...Bit1[A0]Bit
0[B0]. The arrangement of the data in the each
byte is that the MSB is the first received bit and is
the first transmitted bit. The first byte read is the
first byte received, and the first byte sent is the first
byte transmitted. If you read two bytes from the E
buffer, you will get the following arrangement:
A[7]B[7]A[6]B[6]....A[0]B[0].
39

CS8415A-CS PDF文件相關(guān)型號(hào)

CS8415A-CZ,CS8415A-IZ

CS8415A-CS 產(chǎn)品屬性

  • Cirrus Logic

  • 音頻 DSP

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