最新免费av在线观看,亚洲综合一区成人在线,中文字幕精品无码一区二区三区,中文人妻av高清一区二区,中文字幕乱偷无码av先锋

CS8415A-CS Datasheet

  • CS8415A-CS

  • Cirrus Logic [96 kHz DIGITAL AUDIO INTERFACE RECEIVER]

  • CIRRUS

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

CS8415A
8.6
7
0
Interrupt 2 Status (08h) (Read Only)
6
0
5
0
4
0
3
DETU
2
0
1
QCH
0
0
For all bits in this register, a 鈥?鈥?means the associated interrupt condition has occurred at least once since the register
was last read. A 鈥?鈥?means the associated interrupt condition has NOT occurred since the last reading of the register.
Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true.
Status bits that are masked off in the associated mask register will always be 鈥?鈥?in this register. This register defaults
to 00h.
DETU - D to E U-buffer transfer interrupt. (Block Mode only)
The source of this bit is true during the D to E buffer transfer in the U bit buffer management
process.
QCH - A new block of Q-subcode data is available for reading.
The data must be completely read within 588 AES3 frames after the interrupt occurs to avoid
corruption of the data by the next block.
8.7
7
0
Interrupt 1 Mask (09h)
6
OSLIPM
5
0
4
0
3
0
2
DETCM
1
0
0
RERRM
The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is unmasked,
meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked,
meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre-
sponding bits in Interrupt 1 register. This register defaults to 00h.
8.8
7
0
0
Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB(0Bh)
6
OSLIP1
OSLIP0
5
0
0
4
0
0
3
0
0
2
DETC1
DETC0
1
0
0
0
RERR1
RERR0
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to
set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin be-
comes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active
on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the in-
terrupt condition. Be aware that the active level(Actice High or Low) only depends on the INT[1:0] bits. These regis-
ters default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
8.9
7
0
Interrupt 2 Mask (0Ch)
6
0
5
0
4
0
3
DETUM
2
0
1
QCHM
0
0
The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the error is unmasked,
meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked,
meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre-
23

CS8415A-CS PDF文件相關(guān)型號(hào)

CS8415A-CZ,CS8415A-IZ

CS8415A-CS 產(chǎn)品屬性

  • Cirrus Logic

  • 音頻 DSP

CS8415A-CS相關(guān)型號(hào)PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號(hào)推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！