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CS8415A-CS Datasheet

  • CS8415A-CS

  • Cirrus Logic [96 kHz DIGITAL AUDIO INTERFACE RECEIVER]

  • 733.62KB

  • CIRRUS

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CS8415A
8. CONTROL PORT REGISTER BIT DEFINITIONS
8.1
7
SWCLK
Control 1(01h)
6
0
5
MUTESAO
4
0
3
0
2
INT1
1
INT0
0
0
SWCLK - Controls output of OMCK on RMCK when PLL loses lock
Default = 鈥?鈥?/div>
0 - RMCK default function
1 - OMCK output on RMCK pin
MUTESAO - Mute control for the serial audio output port
Default = 鈥?鈥?/div>
0 - Disabled
1 - Enabled
INT1:0 - Interrupt output pin (INT) control
Default = 鈥?0鈥?/div>
00 - Active high; high output indicates interrupt condition has occurred
01 - Active low, low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved
8.2
7
0
Control 2 (02h)
6
HOLD1
5
HOLD0
4
RMCKF
3
MMR
2
MUX2
1
MUX1
0
MUX0
HOLD1:0 - Determine how received audio sample is affected when a receiver error occurs
Default = 鈥?0鈥?/div>
00 - Hold the last valid audio sample
01 - Replace the current audio sample with 00 (mute)
10 - Do not change the received audio sample
11 - Reserved
RMCKF - Select recovered master clock output pin frequency.
Default = 鈥?鈥?/div>
0 - RMCK is equal to 256 * Fs
1 - RMCK is equal to 128 * Fs
MMR - Select AES3 receiver mono or stereo operation
Default = 鈥?鈥?/div>
0 - Normal stereo operation
1 - A and B subframes treated as consecutive samples of one channel of data.
Data is duplicated to both left and right parallel outputs of the AES receiver block.
The sample rate (Fs) is doubled compared to MMR=0
20

CS8415A-CS PDF文件相關(guān)型號(hào)

CS8415A-CZ,CS8415A-IZ

CS8415A-CS 產(chǎn)品屬性

  • Cirrus Logic

  • 音頻 DSP

CS8415A-CS相關(guān)型號(hào)PDF文件下載

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