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CS8415A-CS Datasheet

  • CS8415A-CS

  • Cirrus Logic [96 kHz DIGITAL AUDIO INTERFACE RECEIVER]

  • CIRRUS

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CS8415A
7. CONTROL PORT REGISTER SUMMARY
Addr
(HEX)
01
02
04
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14-1D
1E
20-37
7F
Function
Control 1
Control 2
Clock Source Control
Serial Output Format
Interrupt 1 Status
Interrupt 2 Status
Interrupt 1 Mask
Interrupt 1 Mode (MSB)
Interrupt 1 Mode (LSB)
Interrupt 2 Mask
Interrupt 2 Mode (MSB)
Interrupt 2 Mode (LSB)
Receiver CS Data
Receiver Errors
Receiver Error Mask
CS Data Buffer Control
U Data Buffer Control
Q sub-code Data
OMCK/RMCK Ratio
C or U Data Buffer
ID and Version
7
SWCLK
0
0
SOMS
0
0
0
0
0
0
0
0
AUX3
0
0
0
0
6
0
HOLD1
RUN
SOSF
OSLIP
0
OSLIPM
OSLIP1
OSLIP0
0
0
0
AUX2
QCRC
QCRCM
0
0
5
MUTESAO
HOLD0
0
SORES1
0
0
0
0
0
0
0
0
AUX1
CCRC
CCRCM
BSEL
0
4
0
RMCKF
0
SORES0
0
0
0
0
0
0
0
0
AUX0
UNLOCK
UNLOCKM
CBMR
0
3
0
MMR
0
SOJUST
0
DETU
0
0
0
DETUM
DETU1
DETU0
PRO
V
VM
DETCI
0
2
INT1
MUX2
0
SODEL
DETC
0
DETCM
DETC1
DETC0
0
0
0
AUDIO
CONF
CONFM
0
0
1
INT0
MUX1
0
SOSPOL
0
QCH
0
0
0
QCHM
QCH1
QCH0
COPY
BIP
BIPM
CAM
DETUI
0
0
MUX0
1
SOLRPOL
RERR
0
RERRM
RERR1
RERR0
0
0
0
ORIG
PAR
PARM
CHS
0
ORR7
ORR6
ORR5
ORR4
ORR3
ORR2
ORR1
ORR0
ID3
ID2
ID1
ID0
VER3
VER2
VER1
VER0
Table 1. Control Register Map Summary
7.1
Memory Address Pointer (MAP)
7
INCR
6
MAP6
5
MAP5
4
MAP4
3
MAP3
2
MAP2
1
MAP1
0
MAP0
INCR - Auto Increment Address Control Bit
Default = 鈥?鈥?/div>
0 - Disabled
1 - Enabled
MAP6:MAP0 - Register address
Note:
Reserved registers must not be written to during normal operation. Some reserved registers are used for
test modes, which can completely alter the normal operation of the CS8415A.
19

CS8415A-CS PDF文件相關(guān)型號(hào)

CS8415A-CZ,CS8415A-IZ

CS8415A-CS 產(chǎn)品屬性

  • Cirrus Logic

  • 音頻 DSP

CS8415A-CS相關(guān)型號(hào)PDF文件下載

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