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CS8415A-CS Datasheet

  • CS8415A-CS

  • Cirrus Logic [96 kHz DIGITAL AUDIO INTERFACE RECEIVER]

  • CIRRUS

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CS8415A
4. SERIAL AUDIO OUTPUT PORT
A 3-wire serial audio output port is provided. The
port can be adjusted to suit the attached device
setting the control registers. The following param-
eters are adjustable: master or slave, serial clock
frequency, audio data resolution, left or right justifi-
cation of the data relative to left/right clock, option-
al one-bit cell delay of the first data bit, the polarity
of the bit clock and the polarity of the left/right
clock. By setting the appropriate control bits, many
formats are possible.
Figure 6 shows a selection of common output for-
mats, along with the control bit settings. It should
be noted that in right justified mode, the serial au-
dio output data is "MSB extended". This means
that in a sub-frame where the MSB of the data is
'1', all bits preceding the MSB in the sub-frame will
also be '1'. Conversely, in a sub-frame where the
MSB of the data is '0', all bits preceding the MSB in
the sub-frame will also be '0'.
A special AES3 direct output format is included,
which allows the serial output port access to the V,
U, and C bits embedded in the serial audio data
stream. The P bit is replaced by a Z bit that marks
the start of each block. The received channel sta-
tus block start signal is only available in hardware
mode, as the RCBL pin.
In master mode, the left/right clock and the serial
bit clock are outputs, derived from the recovered
RMCK clock. In slave mode, the left/right clock and
the serial bit clock are inputs. The left/right clock
must be synchronous to the appropriate master
clock, but the serial bit clock can be asynchronous
and discontinuous if required. By appropriate
phasing of the left/right clock and control of the se-
rial clocks, multiple CS8415A鈥檚 can share one se-
rial port. The left/right clock should be continuous,
but the duty cycle can be less than the specified
typical value of 50% if enough serial clocks are
present in each phase to clock all the data bits.
When in slave mode, the serial audio output port
must not be set for right-justified data. When using
the serial audio output port in slave mode with an
OLRCK input which is asynchronous to the incom-
ing AES3 data, then an interrupt bit(OSLIP) is pro-
vided to indicate when repeated or dropped
samples occur.The CS8415A allows immediate
mute of the serial audio output port audio data by
the MUTESAO bit of Control Register 1.
12

CS8415A-CS PDF文件相關(guān)型號(hào)

CS8415A-CZ,CS8415A-IZ

CS8415A-CS 產(chǎn)品屬性

  • Cirrus Logic

  • 音頻 DSP

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