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CS5954AM Datasheet

  • CS5954AM

  • Cypress Semiconductor [USB Controller for NAND Flash]

  • CYPRESS

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ADVANCE
INFORMATION
8.22
CS5954AM Processor Instruction Set Summary
Opcode
Mnemonic
MOV
ADD
ADDC
SUB
SUBB
CMP
AND
TEST
OR
XOR
Jcc
JccL
Rcc
Ccc
Int
SHR
SHL
ROR
ROL
ADDI
SUBI
NOT
NEG
CBW
STI
CLI
STC
CLC
Operands
s,d
s,d
s,d
s,d
s,d
s,d
s,d
s,d
s,d
s,d
c,v
c,d
c
c,d
v
n,d
n,d
n,d
n,d
n,d
n,d
d
d
d
Description
Move s to d
Add s to d
Add s to d with carry
Subtract s from d
Subtract s from d with carry
Compare d with s
AND d with s
Bit test d with s
OR d with s
XOR d with s
Jump relative on condition 鈥檆鈥?/div>
Jump absolute on condition 鈥檆鈥?/div>
Return on condition 鈥檆鈥?/div>
Call subroutine on condition 鈥檆鈥?/div>
Software interrupt
Shift right out of carry
Shift left into carry
Rotate right
Rotate left
Add immediate
Subtract immediate
1鈥檚 complement
2鈥檚 complement
Sign-extend d(7:0) to d(15:0)
Enable interrupts
Disable interrupts
Set carry
Clear carry
MSb
0000 ssss ssdd dddd
0001 ssss ssdd dddd
0010 ssss ssdd dddd
0011 ssss ssdd dddd
0100 ssss ssdd dddd
0101 ssss ssdd dddd
0110 ssss ssdd dddd
0111 ssss ssdd dddd
1000 ssss ssdd dddd
1001 ssss ssdd dddd
1100 cccc 0ooo oooo
1100 cccc 10dd dddd
1100 cccc 1001 0111
1010 cccc 10dd dddd
1010 0000 0vvv vvvv
1101 000n nndd dddd
1101 001n nndd dddd
1101 010n nndd dddd
1101 011n nndd dddd
1101 100n nndd dddd
1101 101n nndd dddd
1101 1110 00dd dddd
1101 1110 01dd dddd
1101 1110 10dd dddd
1101 1111 1100 0000
1101 1111 1100 0001
1101 1111 1100 0010
1101 1111 1100 0011
Opcode field descriptions
Field
S
D
C
O
V
N
Description
Source
Destination
Condition code
Signed offset
Interrupt vector
Count value -1
Addressing mode
Register
Immediate
Direct
Indirect
Indirect with Auto Increment
Indirect with Index
0
0
1
0
1
1
5
0
1
0
1
0
1
4
r
1
b/w
b/w
b/w
b/w
3
r
1
1
r
r
r
2
r
1
1
r
r
r
1
LSb
Flags
Affected
None
Z,C,O,S
Z,C,O,S
Z,C,O,S
Z,C,O,S
Z,C,O,S
Z,S
Z,S
Z,S
Z,S
None
None
None
None
None
Z,C,S
Z,C,S
Z,C,S
Z,C,S
Z,S
Z,S
Z,S
Z,O,C,S
Z,S
None
None
C
C
CS5954AM
Clock
Cycles
5
5
5
5
5
5
5
5
5
5
3
4
7
7
7
4
4
4
4
4
4
4
4
4
3
3
3
3
Notes
41, 42
41, 42
41, 42
41, 42
41, 42
41, 42
41, 42
41, 42
41, 42
41, 42
42
42
42
42
42
41, 42, 43
41, 42, 43
41, 42, 43
41, 42, 43
42
42
42
42
42
42
42
42
42
Clock
Adder
0
0
1
1
2
3
0
r
1
1
r
r
r
b/w: 鈥?鈥?= byte access, 鈥?鈥?= word access.
Indirect with auto-increment and byte-wide indirect addressing is illegal with R15.
Notes:
41. The number in the 鈥渃lock cycles鈥?column reflects the number of clock cycles for register or immediate accesses. For each occurrence of other types of accesses,
include the appropriate 鈥渃lock adder鈥?as listed in the Addressing Modes table below.
42. All clock cycle values assume zero wait-states.
43. A shift of one is done in four clock cycles, each additional shift adds two more clock cycles.
Document #: 38-08025 Rev. **
Page 36 of 44

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