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CS5954AM Datasheet

  • CS5954AM

  • Cypress Semiconductor [USB Controller for NAND Flash]

  • CYPRESS

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ADVANCE
INFORMATION
8.9
Addressing Modes
CS5954AM
This section describes in detail the six-operand field bits referred to in the previous section as
source
and
destination.
Bear in
mind that although the discussion refers to bits 0 through 5, the same bit definitions apply to the 鈥渟ource鈥?operand field, bits 6
through 11. These are the basic addressing modes in the CS5954AM processor.
Mode
Register
Immediate
Direct
Indirect
Indirect with Auto Increment
[29]
Indirect with Index
5
0
0
1
0
1
1
4
0
1
0
1
0
1
3
r
1
b/w
[28]
b/w
[28]
b/w
[28]
b/w
[28]
2
r
1
1
r
r
r
1
r
1
1
r
r
r
0
r
1
1
r
r
r
8.10
Register Addressing
In register addressing, any one of registers R0鈥揜15 can be selected using bits 0鈥?. If register addressing is used, operands are
always 16-bit operands, since all registers are 16-bit registers. For example, an instruction using register R7 as an operand would
fill the operand field as follows.
Bits
Register Operand
5
0
4
0
3
0
2
1
1
1
0
1
8.11
Immediate Addressing
In Immediate Addressing, the instruction word is immediately followed by the source operand. For example, the operand field
would be filled as follows.
[30]
Bits
Operand field
5
0
4
1
3
1
2
1
1
1
0
1
8.12
Direct Addressing
In Direct Addressing, the word following the instruction word is used as an address into RAM. Again, the operand can be either
byte or word sized, depending on the state of bit 3 of the operand field. For example, to do a word-wide read from a direct address,
the
source
operand field would be formed as follows.
[31]
Bits
I/O operand
5
1
4
0
3
0
2
1
1
1
0
1
8.13
Indirect Addressing
Indirect addressing is accomplished using address registers R8鈥?5. In Indirect addressing, the operand is found at the memory
address pointed to by the register. Since only eight address registers exist, only three bits are required to select an address
register. For example, register R10 (binary 1010) can be selected by ignoring bit 3, leaving the bits 010. Bit 3 of the operand field
is then used as the byte/word bit, set to 鈥?鈥?to select word or 鈥?鈥?to select byte addressing. In this example, a byte-wide operand
is selected at the memory location pointed to by register R10.
[32]
Bits
Memory operand
5
0
4
1
3
1
2
0
1
1
0
0
Notes:
28. b/w: 鈥?鈥?for byte-wide access, 鈥?鈥?for word access.
29. Indirect with auto-increment and byte-wide Indirect addressing is illegal with the stack pointer (R15).
30. In immediate addressing, the source operand
must
be 16 bits wide, eliminating the need for a b/w bit.
31. For a memory-to-memory move, the instruction word would be followed by two words, the first being the
source
address and the second being the
destination.
32. For register R15, byte-wide operands are prohibited. If bit 3 is set high, the instruction is decoded differently, as explained at the top of this section.
Document #: 38-08025 Rev. **
Page 30 of 44

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